| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | simul: gather terminals | Tristan Gingold | 2022-07-25 | 1 | -0/+28 |
| * | elab-vhdl_decls: elaborate dot attribute | Tristan Gingold | 2022-07-21 | 1 | -0/+13 |
| * | vhdl-nodes: renaming. | Tristan Gingold | 2022-07-21 | 1 | -3/+3 |
| * | elab-vhdl_decls: elaborate implicit signals | Tristan Gingold | 2022-07-21 | 1 | -2/+23 |
| * | vhdl: preliminary work to elaborat quantities | Tristan Gingold | 2022-07-16 | 1 | -0/+13 |
| * | elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype | Tristan Gingold | 2022-06-09 | 1 | -8/+12 |
| * | synth: handle suspend state declaration and statement | Tristan Gingold | 2022-05-27 | 1 | -0/+7 |
| * | synth: add a flag to force creation of variables | Tristan Gingold | 2022-05-11 | 1 | -5/+13 |
| * | synth: handle shared variable without default value. | Tristan Gingold | 2022-04-04 | 1 | -1/+1 |
| * | synth: handle package instantiation in declarations. Fix #1938 | Tristan Gingold | 2022-01-03 | 1 | -0/+3 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -0/+361 |
 |
index : iCE40/ghdl | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |