| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: rename vhdl.annotations to elab.vhdl_annotations | Tristan Gingold | 2022-09-19 | 1 | -1/+1 |
| * | synth: use areapools | Tristan Gingold | 2022-09-02 | 1 | -1/+12 |
| * | elab-vhdl_context: add iterator for top-level packages | Tristan Gingold | 2022-07-20 | 1 | -0/+14 |
| * | synth: move procedure call copyback values in context | Tristan Gingold | 2022-05-25 | 1 | -2/+11 |
| * | elab-vhdl_context: remove cur_stmt from context | Tristan Gingold | 2022-05-17 | 1 | -7/+0 |
| * | elab-vhdl_values: rename signal_index to signal_index_type | Tristan Gingold | 2022-05-15 | 1 | -1/+1 |
| * | elab-vhdl_context: add get_instance_parent | Tristan Gingold | 2022-05-14 | 1 | -0/+4 |
| * | synth: add current_stmt, minor rework | Tristan Gingold | 2022-05-09 | 1 | -0/+8 |
| * | elab-vhdl_context: introduce signal_index | Tristan Gingold | 2022-05-06 | 1 | -0/+3 |
| * | synth: add debug_bt | Tristan Gingold | 2022-03-08 | 1 | -0/+10 |
| * | synth: add hooks to support elaboration of foreign instances | Tristan Gingold | 2021-11-28 | 1 | -0/+6 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -0/+222 |
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index : iCE40/ghdl | |
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