| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: handle generic mapped packages | Tristan Gingold | 2023-01-05 | 1 | -1/+2 |
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| * | simul: handle force/release signal assignments | Tristan Gingold | 2023-01-03 | 1 | -1/+3 |
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| * | synth: add support of interface subprogram | Tristan Gingold | 2023-01-03 | 1 | -7/+4 |
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| * | synth: elaborate case generate statements | Tristan Gingold | 2023-01-01 | 1 | -0/+11 |
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| * | synth: handle copyback associations in any order. | Tristan Gingold | 2022-10-19 | 1 | -12/+30 |
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| * | synth: simplify elab-vhdl_annotations | Tristan Gingold | 2022-09-19 | 1 | -15/+3 |
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| * | synth: simplify elab-vhdl_annotations | Tristan Gingold | 2022-09-19 | 1 | -189/+31 |
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| * | synth: rename vhdl.annotations to elab.vhdl_annotations | Tristan Gingold | 2022-09-19 | 1 | -0/+1535 |
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index : iCE40/ghdl | |
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