iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
...
*	synth: rework association conversions	Tristan Gingold	2022-09-25	1	-34/+11
\|
*	simul: reuse drivers extraction from elaboration	Tristan Gingold	2022-09-25	1	-71/+19
\|
*	synth-vhdl_stmts: minor renaming	Tristan Gingold	2022-09-18	1	-2/+2
\|
*	simul: handle type conversions in port associations	Tristan Gingold	2022-09-18	1	-11/+17
\|
*	simul: fix resolved association	Tristan Gingold	2022-09-17	1	-1/+1
\|
*	simul: use synth_declarations for processes and procedures	Tristan Gingold	2022-09-17	1	-2/+2
\|
*	synth: factorize code (reuse synth_constant_declaration)	Tristan Gingold	2022-09-17	1	-1/+1
\|
*	simul: handle active attribute	Tristan Gingold	2022-09-16	1	-10/+49
\|
*	simul: improve support of concurrent procedure call	Tristan Gingold	2022-09-16	1	-1/+20
\|
*	simul: handle more signals types	Tristan Gingold	2022-09-15	1	-23/+125
\|
*	simul: factorize code for conversion functions	Tristan Gingold	2022-09-12	1	-19/+6
\|
*	simul: do not consider signal parameters as dynamic values	Tristan Gingold	2022-09-12	1	-0/+1
\|
*	simul: move assertions (not to trigger in case of errors)	Tristan Gingold	2022-09-11	1	-3/+3
\|
*	simul: optimize resolution call only for std_logic	Tristan Gingold	2022-09-11	1	-5/+11
\|
*	synth: fix and add checks for memory management.	Tristan Gingold	2022-09-10	1	-6/+17
\|
*	simul: add support for protected objects	Tristan Gingold	2022-09-08	1	-1/+9
\|
*	elab-vhdl_values: factorize code	Tristan Gingold	2022-09-07	1	-2/+2
\|
*	simul: do not propagate errors from resolution function	Tristan Gingold	2022-09-07	1	-0/+3
\|
*	synth: handle generics in blocks	Tristan Gingold	2022-09-06	1	-1/+3
\|
*	simul: add an hook to display report/assert message	Tristan Gingold	2022-09-06	1	-14/+50
\|
*	synth: use areapools	Tristan Gingold	2022-09-02	1	-84/+105
\|
*	synth: factorize code for tracing statements execution	Tristan Gingold	2022-09-02	1	-3/+7
\|
*	simul-vhdl_simul: simplify procedure connect	Tristan Gingold	2022-08-26	1	-41/+22
\|
*	simul: handle connections of records	Tristan Gingold	2022-08-25	1	-1/+18
\|
*	simul: improve support of float signals	Tristan Gingold	2022-08-24	1	-3/+7
\|
*	simul: handle conversions and associations with constants	Tristan Gingold	2022-08-24	1	-43/+373
\|
*	simul: simplify code	Tristan Gingold	2022-08-23	1	-16/+4
\|
*	simul: factorize code to compute number of sources	Tristan Gingold	2022-08-23	1	-119/+3
\|
*	simul: add extra drivers for ports without sources	Tristan Gingold	2022-08-23	1	-4/+65
\|
*	simul-vhdl_simul: handle waveforms in signal assignments	Tristan Gingold	2022-08-21	1	-40/+47
\|
*	simul: rework assertions execution and error handling	Tristan Gingold	2022-08-21	1	-3/+4
\|
*	simul: handle concurrent procedure calls (WIP)	Tristan Gingold	2022-08-21	1	-15/+95
\|
*	simul: handle after clauses in signal assignment	Tristan Gingold	2022-08-21	1	-70/+93
\|
*	simul-vhdl_simul: add support for PSL directives	Tristan Gingold	2022-08-20	1	-10/+252
\|
*	simul: handle resolved signals (WIP)	Tristan Gingold	2022-08-19	1	-42/+295
\|
*	ghdlsimul: add an option to debug before elaboration	Tristan Gingold	2022-08-18	1	-3/+3
\|
*	simul: handle individual associations	Tristan Gingold	2022-08-17	1	-2/+9
\|
*	simul: add create_connects	Tristan Gingold	2022-08-17	1	-1/+92
\|
*	simul: create terminals (WIP)	Tristan Gingold	2022-08-17	1	-6/+49
\|
*	src/simul: rewrite of ghdl/simul based on synth	Tristan Gingold	2022-07-24	1	-0/+1992