| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | simul: handle conversions and associations with constants | Tristan Gingold | 2022-08-24 | 1 | -27/+26 | |
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| * | simul: factorize code to compute number of sources | Tristan Gingold | 2022-08-23 | 1 | -0/+35 | |
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| * | simul: add extra drivers for ports without sources | Tristan Gingold | 2022-08-23 | 1 | -10/+76 | |
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| * | simul: handle individual associations | Tristan Gingold | 2022-08-17 | 1 | -2/+7 | |
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| * | simul: add create_connects | Tristan Gingold | 2022-08-17 | 1 | -37/+38 | |
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| * | simul: create terminals (WIP) | Tristan Gingold | 2022-08-17 | 1 | -1/+2 | |
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| * | simul: gather terminals | Tristan Gingold | 2022-07-25 | 1 | -0/+29 | |
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| * | src/simul: rewrite of ghdl/simul based on synth | Tristan Gingold | 2022-07-24 | 1 | -0/+677 | |
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index : iCE40/ghdl | |
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