iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl08: add support of case-generate statement	Tristan Gingold	2016-07-07	1	-3/+8
*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	1	-15/+39
*	PSL: add counters, generate rti and add --psl-report	Tristan Gingold	2016-03-18	1	-6/+31
*	grt rtis_addr: handle B1 ranges.	Tristan Gingold	2016-01-25	1	-5/+30
*	Pass signal values to interfaces. 'sigptr' optimization.	Tristan Gingold	2015-12-18	1	-1/+6
*	grt: add --list-features, and --has-feature	Tristan Gingold	2015-09-14	1	-2/+3
*	grt-disp_rti: fix thinko (no blocks for if-generate).	Tristan Gingold	2015-01-15	1	-2/+5
*	Handle vhdl08 if generate statements	Tristan Gingold	2015-01-07	1	-31/+22
*	Rework for vhdl08 generate: change rtis.	Tristan Gingold	2015-01-04	1	-15/+41
*	rtis: add source location for blocks and object. Use them in fst dumper.	Tristan Gingold	2014-12-13	1	-0/+29
*	grt-disp_rti: disp alias kind.	Tristan Gingold	2014-12-10	1	-4/+6
*	grt-disp_rti.adb: disp array of enum as strings (when possible).	Tristan Gingold	2014-12-10	1	-40/+97
*	Move files and dirs from translate/	Tristan Gingold	2014-11-05	1	-0/+1080