| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ghdlsynth: add option to select the output format. | Tristan Gingold | 2019-07-01 | 1 | -6/+16 |
| * | ghdldrv: add comments, analyze files for --synth/-e | Tristan Gingold | 2019-07-01 | 1 | -1/+3 |
| * | vhdl: move annotations from simul to vhdl. | Tristan Gingold | 2019-06-29 | 1 | -4/+4 |
| * | ghdldrv: refactoring - share more code, isolate ghdlsynth from ghdlsimul. | Tristan Gingold | 2019-06-29 | 1 | -16/+16 |
| * | Error_Msg_Option: do not raise exception. | Tristan Gingold | 2019-06-25 | 1 | -2/+3 |
| * | synth: get rid of execution and elaboration. | Tristan Gingold | 2019-06-19 | 1 | -2/+6 |
| * | synth: add disp_vhdl. | Tristan Gingold | 2019-05-21 | 1 | -2/+7 |
| * | vhdl: move canon to a vhdl child package. | Tristan Gingold | 2019-05-05 | 1 | -3/+3 |
| * | synth: add --disp-noinline | Tristan Gingold | 2019-04-16 | 1 | -4/+22 |
| * | ghdldrv: Cmd argument of Perform_Action is now in. | Tristan Gingold | 2018-12-16 | 1 | -2/+2 |
| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -2/+2 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+118 |
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index : iCE40/ghdl | |
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