iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	ghdlsimul: fix warning.	Tristan Gingold	2019-06-30	1	-1/+1
*	vhdl: move annotations from simul to vhdl.	Tristan Gingold	2019-06-29	1	-3/+3
*	ghdldrv: refactoring - share more code, isolate ghdlsynth from ghdlsimul.	Tristan Gingold	2019-06-29	1	-57/+3
*	Add simple_IO - to be used instead of Text_IO.	Tristan Gingold	2019-05-19	1	-5/+3
*	vhdl: move iirs_utils to vhdl.utils	Tristan Gingold	2019-05-06	1	-2/+2
*	vhdl: move std_standard package to vhdl child.	Tristan Gingold	2019-05-05	1	-3/+3
*	vhdl: move configuration package as a vhdl child.	Tristan Gingold	2019-05-05	1	-4/+4
*	vhdl: move canon to a vhdl child package.	Tristan Gingold	2019-05-05	1	-5/+5
*	simul: fix handling of time resolution.	Tristan Gingold	2019-01-06	1	-2/+3
*	ghdl_simul: adjust after ghdlcomp change.	Tristan Gingold	2018-08-10	1	-5/+13
*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-17/+17
*	Annotations: minor reformating.	Tristan Gingold	2017-11-19	1	-2/+0
*	ghdl_simul: fix crash on option warning.	Tristan Gingold	2017-11-18	1	-0/+2
*	Add ghdlsynth in ghdl_simul	Tristan Gingold	2017-01-31	1	-1/+5
*	simulation: remove sim_be after previous code factorization.	Tristan Gingold	2016-10-15	1	-6/+6
*	ghdldrv: add functionnal API to compile.	Tristan Gingold	2016-05-07	1	-4/+12
*	Refactoring in simulate in order to link with ortho.	Tristan Gingold	2016-02-20	1	-5/+6
*	simul: return the exit status set by std.env	Tristan Gingold	2016-02-14	1	-0/+2
*	simul: exit with the right status for --has-feature.	Tristan Gingold	2016-02-09	1	-2/+11
*	simul: fix various issues.	Tristan Gingold	2016-01-24	1	-1/+1
*	Fix ghdl_simul build.	Tristan Gingold	2015-11-30	1	-2/+2
*	ghdlsimul: adjust after use of name for block_specification.	Tristan Gingold	2015-01-17	1	-2/+2
*	Move files and dirs from translate/	Tristan Gingold	2014-11-05	1	-0/+209