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* Synthesis of PSL prev function.Tristan Gingold2020-06-022-5/+5
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-023-117/+155
* synth: handle reduction operators. Fix #1342Tristan Gingold2020-05-271-362/+366
* vhdl-nodes: Rename and move shift/rotate predefined functions. Fix #1325Tristan Gingold2020-05-191-37/+37
* synth: handle functional call to numeric_std binary operators. For #1313Tristan Gingold2020-05-161-81/+81
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-203-15/+9
* synth-oper: recognize more operations from std_logic_arith.Tristan Gingold2020-04-121-60/+84
* vhdl: recognize math_real.floor. For #1210Tristan Gingold2020-04-112-339/+341
* vhdl: handle pragma synthesis_on/synthesis_off.Tristan Gingold2020-04-111-180/+184
* vhdl: recognize ext/sxt from std_logic_arith.Tristan Gingold2020-04-111-92/+94
* vhdl: recognize comparaison of std_logic_arith.Tristan Gingold2020-04-111-12/+60
* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-062-97/+108
* python: fix document URI creation on Windows (#1183)Maximilian Köstler2020-03-311-1/+1
* vhdl: recognize reduce functions in std_logic_misc.Tristan Gingold2020-03-281-0/+12
* synth: handle ieee.numeric_std.to_01Tristan Gingold2020-03-222-283/+288
* vhdl: recognize minimum/maximum in numeric_std. For #1168Tristan Gingold2020-03-211-164/+176
* python/setup.py: add missing dependency.Tristan Gingold2020-03-211-0/+6
* synth: handle more operations from synsopsys packages.Tristan Gingold2020-03-141-77/+79
* std_names: add *_reduce names.Tristan Gingold2020-03-131-183/+189
* vhdl: recognize more std_logic_arith operations.Tristan Gingold2020-03-131-0/+32
* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-112-183/+188
* vhdl: recognize mod/rem operators.Tristan Gingold2020-03-101-162/+174
* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-103-169/+179
* python: update setup.py to install ghdl-lsTristan Gingold2020-03-092-10/+35
* Import vhdl_langserver from ghdl-language-serverTristan Gingold2020-03-0911-0/+1510
* [PATCH] Add names for synopsys packages.Tristan Gingold2020-03-032-224/+228
* Set version to 1.0-devTristan Gingold2020-02-281-1/+1
* Release 0.37Tristan Gingold2020-02-281-1/+1
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-182-405/+415
* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-301-205/+209
* synth: handle matching comparisons. Fix #1109Tristan Gingold2020-01-241-90/+126
* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-71/+72
* synth: handle more signed operations. For #1101Tristan Gingold2020-01-191-140/+144
* vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077Tristan Gingold2020-01-111-77/+85
* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-103-235/+238
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-25/+28
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-313-101/+126
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-86/+90
* ams-vhdl: add frequency function, minor fixes.Tristan Gingold2019-12-301-180/+181
* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-302-235/+249
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-283-741/+1004
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-262-13/+21
* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-242-345/+348
* vhdl: recognize sin and cos from math_real.Tristan Gingold2019-11-262-225/+229
* synth: preliminary work to support intrinsic procedures.Tristan Gingold2019-11-141-172/+175
* files_map-editor: add Copy_Source_File.Tristan Gingold2019-11-061-0/+2
* files_map: add Discard_Source_File, Free_Source_File,Tristan Gingold2019-11-061-0/+3
* files_map-editor: turn Replace_Text to a function.Tristan Gingold2019-11-061-0/+4
* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-062-375/+378
* Add names for formal input gates/attributes.Tristan Gingold2019-10-301-167/+173
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