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* python: update setup.py to install ghdl-lsTristan Gingold2020-03-092-10/+35
* Import vhdl_langserver from ghdl-language-serverTristan Gingold2020-03-0911-0/+1510
* [PATCH] Add names for synopsys packages.Tristan Gingold2020-03-032-224/+228
* Set version to 1.0-devTristan Gingold2020-02-281-1/+1
* Release 0.37Tristan Gingold2020-02-281-1/+1
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-182-405/+415
* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-301-205/+209
* synth: handle matching comparisons. Fix #1109Tristan Gingold2020-01-241-90/+126
* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-71/+72
* synth: handle more signed operations. For #1101Tristan Gingold2020-01-191-140/+144
* vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077Tristan Gingold2020-01-111-77/+85
* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-103-235/+238
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-25/+28
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-313-101/+126
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-86/+90
* ams-vhdl: add frequency function, minor fixes.Tristan Gingold2019-12-301-180/+181
* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-302-235/+249
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-283-741/+1004
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-262-13/+21
* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-242-345/+348
* vhdl: recognize sin and cos from math_real.Tristan Gingold2019-11-262-225/+229
* synth: preliminary work to support intrinsic procedures.Tristan Gingold2019-11-141-172/+175
* files_map-editor: add Copy_Source_File.Tristan Gingold2019-11-061-0/+2
* files_map: add Discard_Source_File, Free_Source_File,Tristan Gingold2019-11-061-0/+3
* files_map-editor: turn Replace_Text to a function.Tristan Gingold2019-11-061-0/+4
* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-062-375/+378
* Add names for formal input gates/attributes.Tristan Gingold2019-10-301-167/+173
* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-131-18/+19
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-112-172/+178
* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-112-6/+16
* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-111-22/+27
* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-102-171/+176
* synth: handle package bodies.Tristan Gingold2019-10-072-302/+304
* vhdl: recognize div operators.Tristan Gingold2019-09-301-90/+96
* vhdl: recognize rotate functions.Tristan Gingold2019-09-222-217/+223
* vhdl: add exit/next flags.Tristan Gingold2019-09-182-95/+115
* vhdl: recognize numeric_std shift_left.Tristan Gingold2019-09-112-217/+223
* vhdl: recognize numeric_std mul.Tristan Gingold2019-09-071-82/+88
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-022-5/+5
* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-021-91/+95
* vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-302-196/+202
* vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-302-109/+118
* synth: handle verification units.Tristan Gingold2019-08-202-245/+253
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-242/+243
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-163-479/+510
* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-163-723/+745
* libghdl: preliminary work to also support synth.Tristan Gingold2019-08-131-0/+1
* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-092-276/+268
* pnodes.py: be strict about comments, refactoring.Tristan Gingold2019-08-071-42/+62
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-072-110/+117
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