| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | ci: run black 20.8b1 | eine | 2020-08-27 | 1 | -2/+2 |
| * | python: execute 'black' | eine | 2020-08-23 | 18 | -957/+727 |
| * | py: adjust blank lines to PEP 8 for vhdl_langserver (#1434) | m-kru | 2020-08-15 | 1 | -0/+2 |
| * | vhdl: recognize more operators for std_logic_unsigned/signed. | Tristan Gingold | 2020-08-07 | 1 | -174/+200 |
| * | vhdl: recognize more std_logic_arith operators. | Tristan Gingold | 2020-08-07 | 2 | -300/+314 |
| * | vhdl: parse and analyze force/release signal assignment statements. | Tristan Gingold | 2020-08-01 | 2 | -273/+296 |
| * | vhdl: add force and release tokens. For #1416 | Tristan Gingold | 2020-08-01 | 2 | -125/+127 |
| * | vhdl: replace base_type with parent_type in nodes | Tristan Gingold | 2020-07-22 | 2 | -5/+5 |
| * | synth: handle std_logic_signed.conv_integer. For ghdl/ghdl-yosys-plugin#126 | Tristan Gingold | 2020-06-19 | 1 | -130/+131 |
| * | vhdl: decode to_x01 (from ieee.std_logic_1164) | Tristan Gingold | 2020-06-19 | 2 | -570/+591 |
| * | vhdl: create default configuration for a vunit. Fix #1372 | Tristan Gingold | 2020-06-15 | 3 | -435/+444 |
| * | vhdl: analyze and synth concurrent statements in vunit. Fix #1366 | Tristan Gingold | 2020-06-12 | 1 | -0/+5 |
| * | Synthesis of PSL prev function. | Tristan Gingold | 2020-06-02 | 2 | -5/+5 |
| * | vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662 | Tristan Gingold | 2020-06-02 | 3 | -117/+155 |
| * | synth: handle reduction operators. Fix #1342 | Tristan Gingold | 2020-05-27 | 1 | -362/+366 |
| * | vhdl-nodes: Rename and move shift/rotate predefined functions. Fix #1325 | Tristan Gingold | 2020-05-19 | 1 | -37/+37 |
| * | synth: handle functional call to numeric_std binary operators. For #1313 | Tristan Gingold | 2020-05-16 | 1 | -81/+81 |
| * | types: introduce Direction_Type, which replaces Iir_Direction. | Tristan Gingold | 2020-04-20 | 2 | -14/+9 |
| * | synth-oper: recognize more operations from std_logic_arith. | Tristan Gingold | 2020-04-12 | 1 | -60/+84 |
| * | vhdl: recognize math_real.floor. For #1210 | Tristan Gingold | 2020-04-11 | 2 | -339/+341 |
| * | vhdl: handle pragma synthesis_on/synthesis_off. | Tristan Gingold | 2020-04-11 | 1 | -180/+184 |
| * | vhdl: recognize ext/sxt from std_logic_arith. | Tristan Gingold | 2020-04-11 | 1 | -92/+94 |
| * | vhdl: recognize comparaison of std_logic_arith. | Tristan Gingold | 2020-04-11 | 1 | -12/+60 |
| * | vhdl: add scalar_size. Size of scalar types is computed during analysis. | Tristan Gingold | 2020-04-06 | 2 | -97/+108 |
| * | vhdl: recognize reduce functions in std_logic_misc. | Tristan Gingold | 2020-03-28 | 1 | -0/+12 |
| * | synth: handle ieee.numeric_std.to_01 | Tristan Gingold | 2020-03-22 | 2 | -283/+288 |
| * | vhdl: recognize minimum/maximum in numeric_std. For #1168 | Tristan Gingold | 2020-03-21 | 1 | -164/+176 |
| * | synth: handle more operations from synsopsys packages. | Tristan Gingold | 2020-03-14 | 1 | -77/+79 |
| * | std_names: add *_reduce names. | Tristan Gingold | 2020-03-13 | 1 | -183/+189 |
| * | vhdl: recognize more std_logic_arith operations. | Tristan Gingold | 2020-03-13 | 1 | -0/+32 |
| * | vhdl-ieee-std_logic_arith: recognize more conversions. | Tristan Gingold | 2020-03-11 | 2 | -183/+188 |
| * | vhdl: recognize mod/rem operators. | Tristan Gingold | 2020-03-10 | 1 | -162/+174 |
| * | synthesis: add option --vendor-library= for synthesis. | Tristan Gingold | 2020-03-10 | 3 | -169/+179 |
| * | [PATCH] Add names for synopsys packages. | Tristan Gingold | 2020-03-03 | 2 | -224/+228 |
| * | Set version to 1.0-dev | Tristan Gingold | 2020-02-28 | 1 | -1/+1 |
| * | Release 0.37 | Tristan Gingold | 2020-02-28 | 1 | -1/+1 |
| * | vhdl: recognize conversion functions from std_logic_1164 | Tristan Gingold | 2020-02-18 | 2 | -405/+415 |
| * | synth: handle some rotation and shifts. Fix #1077 | Tristan Gingold | 2020-01-30 | 1 | -205/+209 |
| * | synth: handle matching comparisons. Fix #1109 | Tristan Gingold | 2020-01-24 | 1 | -90/+126 |
| * | synth: add id_abs gate. For #1101 | Tristan Gingold | 2020-01-20 | 1 | -71/+72 |
| * | synth: handle more signed operations. For #1101 | Tristan Gingold | 2020-01-19 | 1 | -140/+144 |
| * | vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077 | Tristan Gingold | 2020-01-11 | 1 | -77/+85 |
| * | synth: handle ieee.math_real.round Fix #1075 | Tristan Gingold | 2020-01-10 | 3 | -235/+238 |
| * | ams-vhdl: add support for 'delayed for quantity. | Tristan Gingold | 2019-12-31 | 1 | -25/+28 |
| * | ams-vhdl: handle zoh, ltf and ztf attributes. | Tristan Gingold | 2019-12-31 | 3 | -101/+126 |
| * | ams-vhdl: add simultaneous null statement. | Tristan Gingold | 2019-12-30 | 1 | -86/+90 |
| * | ams-vhdl: add frequency function, minor fixes. | Tristan Gingold | 2019-12-30 | 1 | -180/+181 |
| * | ams-vhdl: check nature for record natures and terminals. | Tristan Gingold | 2019-12-30 | 2 | -235/+249 |
| * | vhdl: improve support of AMS-vhdl (array and record natures, source quantities) | Tristan Gingold | 2019-12-28 | 3 | -741/+1004 |
| * | vhdl: add Has_Delay_Machanism for optional 'inertial' printing. | Tristan Gingold | 2019-12-26 | 2 | -13/+21 |
