| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | testsuite/gna: add a test for #2098 | Tristan Gingold | 2022-06-16 | 2 | -0/+167 | |
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| * | | vhdl-sem.adb(are_trees_equal): handle simple aggregate. | Tristan Gingold | 2022-06-16 | 1 | -14/+12 | |
| | | | | | | | | | Fix #2098 | |||||
| * | | testsuite/gna: add a test for #2065 | Tristan Gingold | 2022-06-16 | 4 | -0/+742 | |
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| * | | vhdl/translate: handle inertial association in recursive instantiation | Tristan Gingold | 2022-06-16 | 2 | -2/+16 | |
| | | | | | | | | | Fix #2065 | |||||
| * | | testsuite/gna: add a test for #2097 | Tristan Gingold | 2022-06-16 | 6 | -0/+209 | |
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| * | | vhdl-sem_names: handle element and subtype attributes for type conv. | Tristan Gingold | 2022-06-16 | 1 | -22/+26 | |
| | | | | | | | | | Fix #2097 | |||||
| * | | vhdl-sem_expr: do not attribute element or subtype attributes as expr. | Tristan Gingold | 2022-06-16 | 1 | -0/+2 | |
| | | | | | | | | | For #2097 | |||||
| * | | testsuite/gna: add a test for #2071 | Tristan Gingold | 2022-06-15 | 4 | -0/+111 | |
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| * | | vhdl: handle 'element in 'range. Fix #2071 | Tristan Gingold | 2022-06-15 | 2 | -23/+104 | |
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| * | | Add comments | Tristan Gingold | 2022-06-15 | 2 | -1/+2 | |
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| * | | testsuite/synth: add a test for #2093 | Tristan Gingold | 2022-06-15 | 3 | -1/+54 | |
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| * | | netlists-rename: handle handle signal instances. Fix #2093 | Tristan Gingold | 2022-06-15 | 3 | -2/+28 | |
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| * | | testsuite/synth: add a test for #2054 | Tristan Gingold | 2022-06-14 | 2 | -0/+27 | |
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| * | | src/synth: add netlists.rename to rename identifiers. Fix #2054 | Tristan Gingold | 2022-06-14 | 4 | -2/+132 | |
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| * | | testsuite/synth: add a test for #2092 | Tristan Gingold | 2022-06-13 | 2 | -0/+36 | |
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| * | | netlists-disp_verilog: do not display blackboxes. Fix #2092 | Tristan Gingold | 2022-06-13 | 1 | -0/+5 | |
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| * | | Merge pull request #2094 from antonblanchard/synth-verilog-blocking | tgingold | 2022-06-13 | 1 | -10/+10 | |
| |\ \ | | | | | | | netlists-disp_verilog: Use blocking assignments in non-clocked blocks | |||||
| | * | | netlists-disp_verilog: Use blocking assignments in non-clocked blocks | Anton Blanchard | 2022-06-13 | 1 | -10/+10 | |
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| * | | testsuite/gna: add a test for #2091 | Tristan Gingold | 2022-06-12 | 3 | -0/+117 | |
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| * | | vhdl: add a parent field to protected_type_declaration. Fix #2091 | Tristan Gingold | 2022-06-12 | 3 | -265/+271 | |
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| * | | testsuite/synth: add a test. close #2080 | Tristan Gingold | 2022-06-12 | 3 | -0/+62 | |
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| * | | testsuite/synth: add a test for #2090 | Tristan Gingold | 2022-06-12 | 2 | -0/+70 | |
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| * | | synth-vhdl_insts: handle actual conversion function. Fix #2090 | Tristan Gingold | 2022-06-12 | 1 | -12/+38 | |
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| * | | testsuite/synth: add a test for #2089 | Tristan Gingold | 2022-06-12 | 2 | -0/+49 | |
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| * | | elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089 | Tristan Gingold | 2022-06-12 | 2 | -7/+18 | |
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| * | | vhdl-nodes: add Inertial_Flag for association_element_by_expression | Tristan Gingold | 2022-06-12 | 7 | -387/+452 | |
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| * | | testsuite/synth: add tests for #2088 | Tristan Gingold | 2022-06-11 | 4 | -0/+117 | |
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| * | | elab-vhdl_types(Synth_Array_Attribute): handle dimension parameter | Tristan Gingold | 2022-06-11 | 1 | -1/+3 | |
| | | | | | | | | | Fix #2088 | |||||
| * | | testsuite/synth: add a test for #2086 | Tristan Gingold | 2022-06-11 | 2 | -0/+35 | |
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| * | | synth-environment(Merge_Dyn_Insert): disable transformation. | Tristan Gingold | 2022-06-11 | 1 | -1/+3 | |
| | | | | | | | | | | | | | Do not transform a Dyn_Insert into a Dyn_Insert_En, to avoid spurious latch detection. For #2086 | |||||
| * | | netlists-memories: handle negation for In_Conjunction. Fix #2086 | Tristan Gingold | 2022-06-11 | 1 | -8/+3 | |
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| * | | synth-vhdl_eval: add support for more operations | Tristan Gingold | 2022-06-11 | 1 | -1/+10 | |
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| * | | vhdl: recognize ieee.math_real.sign, fix is_x recogn. | Tristan Gingold | 2022-06-11 | 9 | -217/+251 | |
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| * | | Merge pull request #2087 from Guiltybyte/support-non-glibc | tgingold | 2022-06-09 | 1 | -1/+1 | |
| |\ \ | | | | | | | Support non glibc Linux systems | |||||
| | * | | deleted pragma messages | Guiltybyte | 2022-06-09 | 1 | -2/+0 | |
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| | * | | Only enable backtrace on linux if glibc is present | Guiltybyte | 2022-06-09 | 1 | -1/+3 | |
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| * | | testsuite/synth: add a test for #2085 | Tristan Gingold | 2022-06-09 | 2 | -0/+35 | |
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| * | | elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype | Tristan Gingold | 2022-06-09 | 7 | -30/+64 | |
| | | | | | | | | | Fix #2085 | |||||
| * | | testsuite/synth: add a test for #2084 | Tristan Gingold | 2022-06-09 | 2 | -0/+23 | |
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| * | | vhdl-annotations: avoid a crash with subtype attribute in array. | Tristan Gingold | 2022-06-09 | 3 | -5/+16 | |
| | | | | | | | | | Fix #2084 | |||||
| * | | testsuite/synth: add a test for #2083 | Tristan Gingold | 2022-06-08 | 2 | -0/+39 | |
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| * | | synth-vhdl_expr.adb: use base type for indexed names. Fix #2083 | Tristan Gingold | 2022-06-08 | 1 | -1/+2 | |
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| * | | synth-vhdl_expr: add an hook for signal attributes | Tristan Gingold | 2022-06-08 | 2 | -0/+11 | |
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| * | | Makefile.in: tentatively use shared-libgcc for ghdl_mcode | Tristan Gingold | 2022-06-08 | 1 | -1/+1 | |
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| * | | synth-vhdl_eval: handle more operations | Tristan Gingold | 2022-06-07 | 1 | -8/+17 | |
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| * | | vhdl-sem: adjust condition to set suspend_state on procedures | Tristan Gingold | 2022-06-07 | 4 | -269/+291 | |
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| * | | elab-vhdl_context: also handle generic subprograms | Tristan Gingold | 2022-06-07 | 1 | -2/+6 | |
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| * | | options.adb: add commands | Tristan Gingold | 2022-06-07 | 1 | -2/+2 | |
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| * | | pyGHDL: regenerate | Tristan Gingold | 2022-06-07 | 1 | -10/+11 | |
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| * | | testsuite/synth: add a test for #2081 | Tristan Gingold | 2022-06-07 | 2 | -0/+25 | |
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index : iCE40/ghdl | |
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