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author | Tristan Gingold <tgingold@free.fr> | 2022-06-07 04:05:01 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-06-07 04:05:01 +0200 |
commit | 12143ffdfa70f798c625f545f3afbee0e940fc1b (patch) | |
tree | a3642f0c8af307733fd67d3c49ee2e956e7c0244 | |
parent | 177546b2cbb41f4a835025631187fb4dcf0c896e (diff) | |
download | ghdl-12143ffdfa70f798c625f545f3afbee0e940fc1b.tar.gz ghdl-12143ffdfa70f798c625f545f3afbee0e940fc1b.tar.bz2 ghdl-12143ffdfa70f798c625f545f3afbee0e940fc1b.zip |
testsuite/synth: add a test for #2081
-rw-r--r-- | testsuite/synth/issue2081/ent.vhdl | 16 | ||||
-rwxr-xr-x | testsuite/synth/issue2081/testsuite.sh | 9 |
2 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/issue2081/ent.vhdl b/testsuite/synth/issue2081/ent.vhdl new file mode 100644 index 000000000..f9fefd528 --- /dev/null +++ b/testsuite/synth/issue2081/ent.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is +end entity; + +architecture a of ent is + signal foo : std_logic_vector(7 downto 0); +begin + process(foo) + begin + if foo /= x"00" then + assert false; + end if; + end process; +end architecture; diff --git a/testsuite/synth/issue2081/testsuite.sh b/testsuite/synth/issue2081/testsuite.sh new file mode 100755 index 000000000..363692cc2 --- /dev/null +++ b/testsuite/synth/issue2081/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +synth ent.vhdl -e > syn_ent.vhdl + +synth_failure -Werror=nowrite ent.vhdl -e + +echo "Test successful" |