| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | ghdlsimul: now based on synth elab | Tristan Gingold | 2022-05-11 | 3 | -102/+119 |
| * | synth: handle text file write | Tristan Gingold | 2022-05-11 | 3 | -0/+93 |
| * | synth: add a flag to force creation of variables | Tristan Gingold | 2022-05-11 | 5 | -9/+21 |
| * | ghdlsynth.adb: remove -E experimental command | Tristan Gingold | 2022-05-10 | 1 | -145/+42 |
| * | synth: add current_stmt, minor rework | Tristan Gingold | 2022-05-09 | 4 | -61/+99 |
| * | testsuite/synth: add a test for #2053 | Tristan Gingold | 2022-05-07 | 3 | -0/+127 |
| * | synth-vhdl_insts: handle interfaces of type interface type. Fix #2053 | Tristan Gingold | 2022-05-07 | 1 | -1/+12 |
| * | testsuite/gna: add a test for #2051 | Tristan Gingold | 2022-05-07 | 4 | -0/+2375 |
| * | vhdl: consider fully static record aggregates. Fix #2051 | Tristan Gingold | 2022-05-07 | 4 | -26/+83 |
| * | ortho/debug: handle aggregates of record-subtype | Tristan Gingold | 2022-05-07 | 3 | -7/+25 |
| * | elab-vhdl_context: introduce signal_index | Tristan Gingold | 2022-05-06 | 3 | -3/+12 |
| * | testsuite/gna: add a test for #2050 | Tristan Gingold | 2022-05-06 | 2 | -0/+25 |
| * | vhdl-sem.adb(are_trees_equal): handle selected element. Fix #2050 | Tristan Gingold | 2022-05-06 | 1 | -0/+4 |
| * | testsuite/gna: add a test for #2048 | Tristan Gingold | 2022-05-03 | 2 | -0/+4 |
| * | vhdl-sem_names: second fix for #2048 | Tristan Gingold | 2022-05-03 | 1 | -1/+2 |
| * | testsuite/synth: add a test for #2049 | Tristan Gingold | 2022-05-02 | 2 | -0/+103 |
| * | synth-vhdl_context: resize table before access. Fix #2049 | Tristan Gingold | 2022-05-02 | 1 | -6/+14 |
| * | testsuite/gna: add a test for #2048 | Tristan Gingold | 2022-05-02 | 2 | -0/+12 |
| * | vhdl-sem_names(sem_selected_by_all_name): avoid a crash | Tristan Gingold | 2022-05-02 | 1 | -0/+4 |
| * | testsuite/gna: add a test for previous commit | Tristan Gingold | 2022-05-02 | 2 | -0/+12 |
| * | vhdl-sem_assocs: avoid a crash after forced analysis | Tristan Gingold | 2022-05-02 | 1 | -0/+5 |
| * | testsuite/synth: add a test for #2046 | Tristan Gingold | 2022-05-02 | 2 | -0/+95 |
| * | netlists: fix incorrect access (realloc). Fix #2046 | Tristan Gingold | 2022-05-02 | 1 | -8/+11 |
| * | elab-vhdl_debug: also print objects in disp_hierarchy | Tristan Gingold | 2022-05-01 | 3 | -59/+140 |
| * | elab-vhdl_objtypes: fix restart of libghdl | Tristan Gingold | 2022-04-30 | 3 | -7/+25 |
| * | synth: avoid a crash after an error | Tristan Gingold | 2022-04-29 | 2 | -0/+19 |
| * | elab-vhdl_insts: use block configuration from configuration | Tristan Gingold | 2022-04-29 | 1 | -3/+6 |
| * | synth: adjust elab-debugger__on.adb | Tristan Gingold | 2022-04-29 | 1 | -8/+4 |
| * | ghdlsynth: add experimental command -E | Tristan Gingold | 2022-04-29 | 1 | -8/+133 |
| * | elab-vhdl_types: do not crash on signal resolver | Tristan Gingold | 2022-04-29 | 1 | -0/+3 |
| * | testsuite/synth: add tests for previous commit (enum comparison) | Tristan Gingold | 2022-04-29 | 2 | -0/+56 |
| * | synth-vhdl_eval: handle all comparisons for enums | Tristan Gingold | 2022-04-29 | 1 | -33/+29 |
| * | testsuite/synth: add new tests for attributes | Tristan Gingold | 2022-04-29 | 3 | -0/+76 |
| * | synth-vhdl_decls: handle attributes on input ports | Tristan Gingold | 2022-04-29 | 1 | -2/+10 |
| * | vhdl-annotations: do not annotate type for signal attributes | Tristan Gingold | 2022-04-29 | 1 | -2/+0 |
| * | options: add -fpragma-translate options (for debug purposes) | Tristan Gingold | 2022-04-29 | 1 | -0/+3 |
| * | ghdldrv: allow --work within files for import command | Tristan Gingold | 2022-04-29 | 1 | -19/+60 |
| * | synth: extract elab-vhdl_debug from elab-debugger | Tristan Gingold | 2022-04-29 | 3 | -465/+662 |
| * | vhdl-nodes: reorder, add iir_kinds_structural_statement | Tristan Gingold | 2022-04-29 | 2 | -20/+36 |
| * | testsuite/synth: add more tests for component | Tristan Gingold | 2022-04-29 | 4 | -0/+136 |
| * | elab-vhdl_insts: handle open unconstrained port association | Tristan Gingold | 2022-04-29 | 1 | -0/+3 |
| * | testsuite/synth: add a test for #2045 | Tristan Gingold | 2022-04-28 | 2 | -0/+43 |
| * | synth-vhdl_stmts: handle static evaluation for cond variable assignment | Tristan Gingold | 2022-04-28 | 1 | -18/+53 |
| * | ghdllib: adjust first line comment (pasto) | Tristan Gingold | 2022-04-28 | 2 | -2/+2 |
| * | NEWS: add an entry for ieee operators | Tristan Gingold | 2022-04-28 | 1 | -0/+2 |
| * | testsuite/synth: add a test for #2043 | Tristan Gingold | 2022-04-28 | 5 | -1/+118 |
| * | netlists-memories: detect simple loop. Fix #2043 | Tristan Gingold | 2022-04-28 | 1 | -3/+10 |
| * | synth-ieee-numeric_std: factorize code | Tristan Gingold | 2022-04-28 | 1 | -14/+5 |
| * | synth-vhdl_eval: handle abs | Tristan Gingold | 2022-04-27 | 3 | -19/+61 |
| * | testsuite/synth: add a test for #2042 | Tristan Gingold | 2022-04-27 | 4 | -0/+108 |
