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*
Merge pull request #2094 from antonblanchard/synth-verilog-blocking
tgingold
2022-06-13
1
-10
/
+10
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netlists-disp_verilog: Use blocking assignments in non-clocked blocks
Anton Blanchard
2022-06-13
1
-10
/
+10
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/
*
testsuite/gna: add a test for #2091
Tristan Gingold
2022-06-12
3
-0
/
+117
*
vhdl: add a parent field to protected_type_declaration. Fix #2091
Tristan Gingold
2022-06-12
3
-265
/
+271
*
testsuite/synth: add a test. close #2080
Tristan Gingold
2022-06-12
3
-0
/
+62
*
testsuite/synth: add a test for #2090
Tristan Gingold
2022-06-12
2
-0
/
+70
*
synth-vhdl_insts: handle actual conversion function. Fix #2090
Tristan Gingold
2022-06-12
1
-12
/
+38
*
testsuite/synth: add a test for #2089
Tristan Gingold
2022-06-12
2
-0
/
+49
*
elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089
Tristan Gingold
2022-06-12
2
-7
/
+18
*
vhdl-nodes: add Inertial_Flag for association_element_by_expression
Tristan Gingold
2022-06-12
7
-387
/
+452
*
testsuite/synth: add tests for #2088
Tristan Gingold
2022-06-11
4
-0
/
+117
*
elab-vhdl_types(Synth_Array_Attribute): handle dimension parameter
Tristan Gingold
2022-06-11
1
-1
/
+3
*
testsuite/synth: add a test for #2086
Tristan Gingold
2022-06-11
2
-0
/
+35
*
synth-environment(Merge_Dyn_Insert): disable transformation.
Tristan Gingold
2022-06-11
1
-1
/
+3
*
netlists-memories: handle negation for In_Conjunction. Fix #2086
Tristan Gingold
2022-06-11
1
-8
/
+3
*
synth-vhdl_eval: add support for more operations
Tristan Gingold
2022-06-11
1
-1
/
+10
*
vhdl: recognize ieee.math_real.sign, fix is_x recogn.
Tristan Gingold
2022-06-11
9
-217
/
+251
*
Merge pull request #2087 from Guiltybyte/support-non-glibc
tgingold
2022-06-09
1
-1
/
+1
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deleted pragma messages
Guiltybyte
2022-06-09
1
-2
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+0
|
*
Only enable backtrace on linux if glibc is present
Guiltybyte
2022-06-09
1
-1
/
+3
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/
*
testsuite/synth: add a test for #2085
Tristan Gingold
2022-06-09
2
-0
/
+35
*
elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype
Tristan Gingold
2022-06-09
7
-30
/
+64
*
testsuite/synth: add a test for #2084
Tristan Gingold
2022-06-09
2
-0
/
+23
*
vhdl-annotations: avoid a crash with subtype attribute in array.
Tristan Gingold
2022-06-09
3
-5
/
+16
*
testsuite/synth: add a test for #2083
Tristan Gingold
2022-06-08
2
-0
/
+39
*
synth-vhdl_expr.adb: use base type for indexed names. Fix #2083
Tristan Gingold
2022-06-08
1
-1
/
+2
*
synth-vhdl_expr: add an hook for signal attributes
Tristan Gingold
2022-06-08
2
-0
/
+11
*
Makefile.in: tentatively use shared-libgcc for ghdl_mcode
Tristan Gingold
2022-06-08
1
-1
/
+1
*
synth-vhdl_eval: handle more operations
Tristan Gingold
2022-06-07
1
-8
/
+17
*
vhdl-sem: adjust condition to set suspend_state on procedures
Tristan Gingold
2022-06-07
4
-269
/
+291
*
elab-vhdl_context: also handle generic subprograms
Tristan Gingold
2022-06-07
1
-2
/
+6
*
options.adb: add commands
Tristan Gingold
2022-06-07
1
-2
/
+2
*
pyGHDL: regenerate
Tristan Gingold
2022-06-07
1
-10
/
+11
*
testsuite/synth: add a test for #2081
Tristan Gingold
2022-06-07
2
-0
/
+25
*
errorout: add nowrite warning. Fix #2081
Tristan Gingold
2022-06-07
5
-8
/
+16
*
testsuite/gna: add one test for #2076
Tristan Gingold
2022-06-06
2
-0
/
+5
*
vhdl-parse.adb: fix uninitialized variable, for #2076
Tristan Gingold
2022-06-06
1
-0
/
+1
*
testsuite/gna: add tests for #2076
Tristan Gingold
2022-06-06
3
-0
/
+34
*
vhdl-sem_names: avoid a crash on incorrect selected name. For #2076
Tristan Gingold
2022-06-06
1
-1
/
+2
*
vhdl-parse: avoid a crash with return identifier. Fox #2076
Tristan Gingold
2022-06-06
1
-1
/
+7
*
synth-vhdl_stmts: fix handling of instantiated subprograms
Tristan Gingold
2022-06-06
1
-1
/
+3
*
synth-vhdl_eval: handle more operations
Tristan Gingold
2022-06-06
1
-1
/
+16
*
synth-vhdl_stmts: handle alias in assignment expression
Tristan Gingold
2022-06-06
3
-2
/
+24
*
vhdl-ieee-math_real: recognize more operations
Tristan Gingold
2022-06-06
3
-230
/
+285
*
synth-vhdl_eval: recognize and handle to_stdulogicvector
Tristan Gingold
2022-06-06
4
-224
/
+241
*
synth-vhdl_eval: handle more operations
Tristan Gingold
2022-06-05
2
-37
/
+112
*
vhdl: recognize more predefined ieee functions and operators
Tristan Gingold
2022-06-05
5
-465
/
+593
*
synth-vhdl_eval: handle more operations (sgn/uns reduce)
Tristan Gingold
2022-06-05
1
-6
/
+16
*
synth-vhdl-eval: handle more operations
Tristan Gingold
2022-06-05
4
-31
/
+272
*
vhdl-ieee-numeric: recognize vector/scalar operations
Tristan Gingold
2022-06-05
3
-296
/
+368
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