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* synth: use note messages for memories (instead of warnings).Tristan Gingold2019-10-194-28/+34
* ghdlsynth.h: add functions.Tristan Gingold2019-10-191-0/+4
* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-181-0/+5
* netlists-memories: check ports.Tristan Gingold2019-10-181-7/+161
* vhdl-prints: add parenthesis around boolean and/or.Tristan Gingold2019-10-181-0/+4
* synth-stmts: ignore EOS in PSL expressions.Tristan Gingold2019-10-181-1/+8
* syn_interning: add get_index.Tristan Gingold2019-10-172-14/+31
* netlists-disp_vhdl: display memories.Tristan Gingold2019-10-171-1/+97
* synth: add netlists-memories to extract memories. Still WIP.Tristan Gingold2019-10-178-18/+553
* netlists: add remove_instance.Tristan Gingold2019-10-162-0/+35
* vhdl: check cover/restrict is followed by a sequence.Tristan Gingold2019-10-164-11/+65
* synth: fix psl cover - test when the final state is reached.Tristan Gingold2019-10-151-3/+14
* vhdl: Add the implicit [*] at start of PSL cover sequence.Tristan Gingold2019-10-153-0/+37
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-155-1/+17
* synth: handle overflow literal.Tristan Gingold2019-10-152-1/+9
* netlists: declare memory gates.Tristan Gingold2019-10-153-3/+215
* synth-expr: handle any discrete_range in aggregate choices.Tristan Gingold2019-10-151-1/+2
* testsuite/synth: add testcase for previous commit.Tristan Gingold2019-10-156-0/+118
* synth-insts: accept architecture instantiation in synth_dependencies.Tristan Gingold2019-10-151-2/+3
* Use Decode_Work_Option in options. Factorize code.Tristan Gingold2019-10-154-25/+11
* testsuite/synth: add a test for --work option within files.Tristan Gingold2019-10-154-0/+75
* ghdlsynth: allow --work= option in the middle of files.Tristan Gingold2019-10-153-1/+48
* testsuite/synth: add a test.Tristan Gingold2019-10-153-1/+68
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-10-143-1/+87
* synth-inference: handle multiple connections.Tristan Gingold2019-10-141-14/+31
* testsuite/synth: add testcases for previous commit.Tristan Gingold2019-10-1413-0/+494
* synth-infere: extract clock from and tree.Tristan Gingold2019-10-141-17/+102
* netlists-dump: do not print name of anonymous parameters.Tristan Gingold2019-10-141-2/+6
* testsuite/synth: add testcase for previous commit.Tristan Gingold2019-10-143-1/+80
* synth-infere: fix partial assignment with clock enable.Tristan Gingold2019-10-141-2/+9
* vhdl-evaluation: handle bit condition operator. Fix #977Tristan Gingold2019-10-131-0/+3
* synth: handle constants for condition operator.Tristan Gingold2019-10-133-1/+20
* synth-stmts: fix thinko (need to adjust type for indexed a 1-bit array).Tristan Gingold2019-10-131-2/+5
* testsuite/synth: add testcase for previous commit.Tristan Gingold2019-10-133-1/+46
* synth-stmts: handle const indexed array.Tristan Gingold2019-10-131-0/+5
* synth-oper: handle const array array concat.Tristan Gingold2019-10-131-16/+41
* synth-oper: add more operations (float div, less for arrays)Tristan Gingold2019-10-131-7/+39
* testsuite/synth: Add testcase for previous commit (missing assoc in call).Tristan Gingold2019-10-133-0/+67
* synth-stmts: improve support for associations in function calls.Tristan Gingold2019-10-131-19/+92
* synth-inst: minor refactoring.Tristan Gingold2019-10-131-3/+2
* synth-oper: handle unsigned unsigned mul.Tristan Gingold2019-10-131-0/+13
* synth-expr: handle integer type conversion.Tristan Gingold2019-10-131-1/+4
* synth-expr: handle range array attribute in slices.Tristan Gingold2019-10-131-42/+74
* vhdl-annotations: handle list of record elements declaration.Tristan Gingold2019-10-131-2/+4
* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-134-20/+31
* netlists-iterators: avoid a crash if no ports.Tristan Gingold2019-10-131-3/+1
* netlists-dump: improve output.Tristan Gingold2019-10-131-9/+28
* netlists-builders: adjust names of dyn_extract ports.Tristan Gingold2019-10-131-2/+2
* Show error on wait without condition (#976)Pepijn de Vos2019-10-131-0/+4
* add record (in)equality (#975)Pepijn de Vos2019-10-131-2/+4
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