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* Add testcase for #1009Tristan Gingold2019-11-062-0/+25
* synth-expr: do subtype conversion in fill_record_aggregate. Fix #1009Tristan Gingold2019-11-061-1/+2
* Add testcase for #1006Tristan Gingold2019-11-063-0/+46
* synth: unshare default value of variables. Fix #1006Tristan Gingold2019-11-062-4/+42
* netlists-cleanup: do not remove the self-instance.Tristan Gingold2019-11-061-0/+2
* synth-stmts: rewrite target_info to clarify memoryTristan Gingold2019-11-051-18/+56
* synth: do more constant propagation (on build2Tristan Gingold2019-11-054-50/+82
* netlists-disp_vhdl: handle truncate to width 1.Tristan Gingold2019-11-051-2/+7
* netlists-memories: truncate wide addresses.Tristan Gingold2019-11-051-11/+9
* synth-oper: simplify code.Tristan Gingold2019-11-051-7/+4
* netlists: add build2_sresize, simplify code.Tristan Gingold2019-11-053-48/+53
* testsuite/synth: fix permissions.Tristan Gingold2019-11-051-0/+0
* synth: extract netlists-folds from netlists-builders.Tristan Gingold2019-11-0511-160/+216
* netlists-dump: indent output.Tristan Gingold2019-11-053-13/+17
* netlists-memories: adjust message.Tristan Gingold2019-11-051-1/+1
* testsuite/synth: add testcase for #1002.Tristan Gingold2019-11-042-0/+26
* netlists: enable expansion.Tristan Gingold2019-11-041-1/+1
* synth-oper: handle constant not.Tristan Gingold2019-11-041-3/+8
* synth-expr: allow constants in discrete rangeTristan Gingold2019-11-041-0/+2
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-11-043-0/+56
* synth-expr: handle vhdl 2008 aggregates (partially).Tristan Gingold2019-11-042-48/+125
* synth-value: export get_bound_length.Tristan Gingold2019-11-041-0/+3
* ghdlmain: simplify code.Tristan Gingold2019-11-041-4/+1
* vhdl-scanner: handle 'synopsys' pragma.Tristan Gingold2019-11-043-16/+19
* ghdlmain: fix deallocation in response file handling.Tristan Gingold2019-11-041-0/+10
* Add doc of the 3 ways to use PSL with GHDL (Implementation of VHDL -> PSL imp...T. Meissner2019-11-031-15/+84
* netlists-expands: expand rol.Tristan Gingold2019-11-031-0/+30
* synth-oper: use build2_uresizeTristan Gingold2019-11-031-16/+2
* netlists-utils: add clog2Tristan Gingold2019-11-032-0/+8
* netlists-builders: add build2_uresize.Tristan Gingold2019-11-032-0/+31
* synth: fix multiport read memories (for issue #1000)Tristan Gingold2019-11-031-1/+3
* testsuite/synth: add a test for ram/rom.Tristan Gingold2019-11-035-0/+154
* testsuite/synth: add test for tgingold/ghdlsynth-beta#56Tristan Gingold2019-11-033-0/+58
* testsuite/synth/memmux01: add a testTristan Gingold2019-11-033-1/+98
* testsuite/synth/var01: add more tests.Tristan Gingold2019-11-038-2/+233
* synth: cap max in synth_slice_suffixTristan Gingold2019-11-031-1/+8
* netlists-expands: rewrite generate_muxes.Tristan Gingold2019-11-031-24/+102
* testsuite/synth: add memmux04 test.Tristan Gingold2019-11-033-1/+75
* netlists-expands: use a safe walk.Tristan Gingold2019-11-031-1/+3
* Install source of std.standard package to respective VHDL standard version su...Torsten Maehne2019-11-021-3/+3
* testsuite/synth: add a test for inout variableTristan Gingold2019-11-013-0/+64
* synth: add support for inout variable interfaces.Tristan Gingold2019-11-012-3/+4
* synth-values: handle value_const for is_equal.Tristan Gingold2019-11-011-0/+5
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-11-013-1/+68
* synth: handle nested if generate statements.Tristan Gingold2019-11-012-21/+29
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-11-013-1/+123
* netlits: fix memidx order.Tristan Gingold2019-11-012-39/+52
* netlists-dump: improve output.Tristan Gingold2019-11-011-10/+11
* testsuite/synth: add a test for dyn_insert expand.Tristan Gingold2019-11-012-1/+71
* netlists-expands: expand dyn_insertTristan Gingold2019-11-012-42/+174
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