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* ci: fix gnat-gpl download URL (#1071)eine2020-01-081-2/+2
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* fix btdi image names (#1070)eine2020-01-072-2/+2
| | | | | | * ci: fix btdi image used in man.sh * ci: fix btdi image used in make.sh
* testsuite: add more tests for #1038Tristan Gingold2020-01-065-0/+106
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* vhdl/translate: handle implicit record-record conversions.Tristan Gingold2020-01-061-12/+1
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* vhdl/translate: minor refactoring.Tristan Gingold2020-01-062-42/+43
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* vhdl: fix multiple reference in trans-chap3.Tristan Gingold2020-01-061-2/+6
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* doc: add internals/ (WIP). Add a part for index.Tristan Gingold2020-01-064-1/+159
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* testsuite: add a case for #1038Tristan Gingold2020-01-062-0/+35
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* vhdl/translate: handle more partially constrained array subtypes. For #1038Tristan Gingold2020-01-063-6/+10
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* Homogenise NEWS.md, conf.py cleanup (#1065)eine2020-01-033-263/+107
| | | | | | | | * homogenise NEWS.md * travis: rename anchor * doc: conf.py cleanup
* testsuite: add cases for #1051Tristan Gingold2020-01-0213-0/+3855
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* vhdl: handle untranslated subtypes for record aggregates. Fix #1051Tristan Gingold2020-01-021-3/+12
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* testsuite/synth: add a test for #1064Tristan Gingold2020-01-023-0/+60
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* synth: handle scalar inout association for subprograms. Fix #1064Tristan Gingold2020-01-021-0/+2
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* testsuite: complete test for #1063Tristan Gingold2020-01-021-2/+6
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* vhdl: fix order of std_ulogic literals. For #1063Tristan Gingold2020-01-021-3/+3
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* testsuite/synth: improve test for previous commit.Tristan Gingold2020-01-012-4/+40
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* synth-disp_vhdl: handle conversion from signed integers.Tristan Gingold2020-01-011-1/+5
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* synth: optimize integer mod for power of 2.Tristan Gingold2020-01-013-0/+31
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* testsuite: add case for #1063Tristan Gingold2020-01-012-0/+22
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* vhdl: evaluate std_logic matching equality. Fix #1063Tristan Gingold2020-01-012-8/+54
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* testsuite/synth: add a case for #1062Tristan Gingold2020-01-013-0/+47
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* vhdl: handle -gGEN=VAL for --synth. Fix #1062Tristan Gingold2020-01-016-23/+213
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* testsuite/synth: add a test for previous commit.Tristan Gingold2019-12-317-0/+202
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* synth-inference: merge reset for sub-nets.Tristan Gingold2019-12-311-1/+16
| | | | For tgingold/ghdlsynth-beta#76
* synth-environment: also optimize mux merge for sub-nets.Tristan Gingold2019-12-313-1/+34
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* netlists-disp_vhdl: display iadff.Tristan Gingold2019-12-312-7/+19
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* Add option for compiling Wishbone VIP for UVVM framework. (#1061)m-kru2019-12-311-0/+6
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* testsuite/vests/vhdl-ams: update tests list.Tristan Gingold2019-12-311-4/+4
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* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-3110-169/+225
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* testsuite/vests/vhdl-ams: update tests lists.Tristan Gingold2019-12-312-40/+40
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* testsuite/vests/vhdl-ams: fix some tests.Tristan Gingold2019-12-312-3/+3
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* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-3117-172/+484
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* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-3012-241/+539
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* ams-vhdl: add frequency function, minor fixes.Tristan Gingold2019-12-307-186/+207
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* testsuite/vests/vhdl-ams: adjust tests lists.Tristan Gingold2019-12-302-35/+35
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* testsuite/vests/vhdl-ams/ashenden: fix some tests.Tristan Gingold2019-12-302-6/+4
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* ams-vhdl: handle record nature end name.Tristan Gingold2019-12-302-0/+5
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* ams-vhdl: improve error recoveryTristan Gingold2019-12-306-61/+92
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* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-306-90/+175
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* ams-vhdl: fix tree consistency for terminal declaration.Tristan Gingold2019-12-302-3/+3
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* testsuite/vets/vhdl-ams: fix syntax.Tristan Gingold2019-12-3014-42/+42
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* ams-vhdl: correctly test and set staticness of dot/integ attributes.Tristan Gingold2019-12-301-8/+7
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* ams-vhdl: print subnature declarations.Tristan Gingold2019-12-301-1/+16
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* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-309-466/+646
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* vhdl-ams: fix tree consistency for subnature declaration.Tristan Gingold2019-12-294-9/+9
| | | | Also fix use and canon for it.
* vhdl-ams: fix overload for simple simultaneous statement.Tristan Gingold2019-12-293-4/+26
| | | | Fix tree consistency for branch quantity declarations.
* testsuite/synth: add test for #1058Tristan Gingold2019-12-293-0/+61
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* synth: handle wire assigned to a static value. Fix #1058Tristan Gingold2019-12-293-9/+104
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* testsuite/vests: add files-ams.txtTristan Gingold2019-12-282-0/+730
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