iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Fix regressions after previous commit.	Tristan Gingold	2020-03-01	1	-0/+5
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*	testsuite/gna: add a test for #1138	Tristan Gingold	2020-03-01	4	-0/+133
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*	vhdl: a function call is not an object. Fix #1138.	Tristan Gingold	2020-03-01	3	-15/+33
\| \| \| \| \| \|	Report a warning (or an error if not relaxed) when a non-object name is used for an array attribute. Also consider subtype attribute as a type name.
*	vhdl-parse: avoid error cascade for 'subtype before 08.	Tristan Gingold	2020-03-01	1	-1/+0
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*	synth: top entity name is not anymore hashed by default.	Tristan Gingold	2020-03-01	6	-83/+138
\| \| \| \|	Use --top-name=hash to get the previous behaviour.
*	synth-insts: add comments, minor refactoring.	Tristan Gingold	2020-02-29	3	-9/+6
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*	testsuite/synth: add test for #1146	Tristan Gingold	2020-02-29	2	-0/+49
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*	synth: handle more physical operators. Fix #1146	Tristan Gingold	2020-02-29	4	-21/+80
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*	synth-static_oper: handle enum inequality.	Tristan Gingold	2020-02-29	1	-0/+3
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*	testsuite/synth: add a reproducer for tgingold/ghdlsynth-beta#87	Tristan Gingold	2020-02-29	3	-0/+70
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*	synth-decls: fix handling of record subtypes.	Tristan Gingold	2020-02-29	1	-1/+14
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*	Adjust version check in ci-run.sh	Tristan Gingold	2020-02-29	1	-4/+5
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*	Set version to 1.0-dev	Tristan Gingold	2020-02-28	2	-2/+2
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*	Release 0.37	Tristan Gingold	2020-02-28	3	-3/+3
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*	vhdl-parse: improve error messages and recovery.	Tristan Gingold	2020-02-27	1	-8/+46
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*	synth: handle file_close.	Tristan Gingold	2020-02-27	3	-10/+31
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*	synth-static_oper: handle to_stdlogicvector_bv	Tristan Gingold	2020-02-27	1	-1/+20
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*	testsuite/synth: add a simple test for std_logic_arith.	Tristan Gingold	2020-02-27	2	-0/+31
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*	std_logic_arith: comment out unused pragmas.	Tristan Gingold	2020-02-27	1	-283/+283
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*	Update copyright years before the release.	Tristan Gingold	2020-02-26	4	-30/+4
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*	testsuite/gna: add test for #1145	Tristan Gingold	2020-02-25	5	-0/+79
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*	vhdl: handle CR+LF for readline in grt. Fix #1145	Tristan Gingold	2020-02-25	3	-23/+65
\| \| \| \| \| \| \|	Previously CR+LF was handled in std.textio.readline. But that doesn't work if CR is at position 128 because we would need to read the next character. Now untruncated_text_read handles CR/CR+LF/LF and calls ungetc if needed.
*	testsuite/synth: add test case for #1140	Tristan Gingold	2020-02-25	3	-0/+118
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*	testsuites/synth: add missing files.	Tristan Gingold	2020-02-23	2	-0/+97
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*	testsuite/synth: add tests for memory ports order.	Tristan Gingold	2020-02-23	3	-2/+32
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*	netlists: rework memories to fix port orders, add a loop.	Tristan Gingold	2020-02-23	7	-46/+85
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*	netlists-memories: also reduce muxes for extract.	Tristan Gingold	2020-02-21	1	-7/+35
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*	testsuite/synth: add a test for #1144	Tristan Gingold	2020-02-21	2	-0/+25
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*	synth-decls: handle alias declaration without subtype indication.	Tristan Gingold	2020-02-21	1	-2/+7
\| \| \| \|	Fix #1144
*	testsuite/synth: add a source for mem01	Tristan Gingold	2020-02-20	2	-0/+31
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*	netlists-memories: factorize code.	Tristan Gingold	2020-02-20	1	-235/+191
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*	netlists-inference: preliminary work to support else in synch code.	Tristan Gingold	2020-02-20	1	-71/+153
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*	netlists: add midff	Tristan Gingold	2020-02-20	3	-0/+47
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*	add build script for termux (#1143)	umarcor	2020-02-20	1	-0/+15
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*	disable backtrace on android (#1142)	umarcor	2020-02-19	1	-1/+1
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*	vhdl: recognize conversion functions from std_logic_1164	Tristan Gingold	2020-02-18	7	-417/+485
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*	synth: rework static predefined function calls.	Tristan Gingold	2020-02-18	3	-152/+224
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*	synth: handle file_open.	Tristan Gingold	2020-02-18	3	-0/+48
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*	testsuite/synth: adjust testcase #1078	Tristan Gingold	2020-02-18	1	-1/+1
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*	synth-environment: handle unassigned outputs.	Tristan Gingold	2020-02-18	1	-6/+8
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*	netlists-cleanup: refactoring.	Tristan Gingold	2020-02-18	1	-12/+17
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*	testsuite/synth: add a test for previous commit.	Tristan Gingold	2020-02-18	3	-1/+49
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*	synth-insts: handle slices in individual associations.	Tristan Gingold	2020-02-18	1	-0/+21
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*	testsuite/synth: merge ram01 to mem01, add NOTES.txt	Tristan Gingold	2020-02-18	9	-17/+25
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*	testsuite/synth: add test for #1139	Tristan Gingold	2020-02-18	4	-0/+149
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*	vhdl-sem_scopes: handle anonymous signal declarations.	Tristan Gingold	2020-02-18	1	-1/+2
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*	vhdl-configuration: ignore configuration for top_level_entity.	Tristan Gingold	2020-02-18	1	-4/+4
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*	synth-expr: handle anonymous signal declarations.	Tristan Gingold	2020-02-18	2	-6/+10
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*	testsuite/gna: add tests for previous commit.	Tristan Gingold	2020-02-17	6	-0/+168
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*	vhdl-sem_assocs: recurse for individual associations.	Tristan Gingold	2020-02-17	1	-23/+64
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