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author | Tristan Gingold <tgingold@free.fr> | 2020-02-18 18:50:13 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-18 18:50:13 +0100 |
commit | ec2e697a0082f5c08621e9118917105472bce718 (patch) | |
tree | a60d3a00c756eddd9aeb8f959319e2ba0937bd7c | |
parent | b3d54b7ac3187da2803b4b1ddc1b34170a92bf13 (diff) | |
download | ghdl-ec2e697a0082f5c08621e9118917105472bce718.tar.gz ghdl-ec2e697a0082f5c08621e9118917105472bce718.tar.bz2 ghdl-ec2e697a0082f5c08621e9118917105472bce718.zip |
testsuite/synth: add a test for previous commit.
-rw-r--r-- | testsuite/synth/iassoc01/iassoc04.vhdl | 20 | ||||
-rw-r--r-- | testsuite/synth/iassoc01/tb_iassoc04.vhdl | 28 | ||||
-rwxr-xr-x | testsuite/synth/iassoc01/testsuite.sh | 2 |
3 files changed, 49 insertions, 1 deletions
diff --git a/testsuite/synth/iassoc01/iassoc04.vhdl b/testsuite/synth/iassoc01/iassoc04.vhdl new file mode 100644 index 000000000..bddaa94a8 --- /dev/null +++ b/testsuite/synth/iassoc01/iassoc04.vhdl @@ -0,0 +1,20 @@ +entity riassoc04 is + port (v : bit_vector (7 downto 0); + res : out bit); +end riassoc04; + +architecture behav of riassoc04 is +begin + res <= v(0) or v(4); +end behav; + +entity iassoc04 is + port (a, b : bit_vector (3 downto 0); + res : out bit); +end iassoc04; + +architecture behav of iassoc04 is +begin + inst : entity work.riassoc04 + port map (v (7 downto 4) => a, v (3 downto 0) => b, res => res); +end behav; diff --git a/testsuite/synth/iassoc01/tb_iassoc04.vhdl b/testsuite/synth/iassoc01/tb_iassoc04.vhdl new file mode 100644 index 000000000..1da32a469 --- /dev/null +++ b/testsuite/synth/iassoc01/tb_iassoc04.vhdl @@ -0,0 +1,28 @@ +entity tb_iassoc04 is +end tb_iassoc04; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_iassoc04 is + signal a, b : bit_vector (3 downto 0); + signal res : bit; +begin + dut: entity work.iassoc04 + port map (a, b, res); + + process + begin + a <= "0001"; + b <= "0000"; + wait for 1 ns; + assert res = '1' severity failure; + + a <= "0000"; + b <= "0000"; + wait for 1 ns; + assert res = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/iassoc01/testsuite.sh b/testsuite/synth/iassoc01/testsuite.sh index 15f76c252..b1ed1293f 100755 --- a/testsuite/synth/iassoc01/testsuite.sh +++ b/testsuite/synth/iassoc01/testsuite.sh @@ -2,7 +2,7 @@ . ../../testenv.sh -for t in iassoc01 iassoc02 iassoc03; do +for t in iassoc01 iassoc02 iassoc03 iassoc04; do analyze pkg.vhdl $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |