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* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-0617-393/+559
* Move Size_Type from areapools to types.Tristan Gingold2020-04-062-5/+7
* grt/ghdl_main: add comments.Tristan Gingold2020-04-061-0/+7
* Add compatibility with LLVM-10. (#1192)Björn Esser2020-04-062-8/+9
* grt: slightly simplify the interface.Tristan Gingold2020-04-024-21/+7
* Remove deprecated src/mhdlsimTristan Gingold2020-04-023-135/+0
* grt: add code to support systemc co-simulation.Tristan Gingold2020-04-0210-48/+147
* synth: more cleanup (and use of valtyp).Tristan Gingold2020-04-0214-391/+358
* testsuite/synth: add a test for #1186Tristan Gingold2020-04-022-0/+23
* synth: handle reals in parameters. Fix #1186Tristan Gingold2020-04-021-12/+25
* synth: rework - use valtyp for expressions.Tristan Gingold2020-04-0219-933/+1029
* testsuite/synth: use harness.Tristan Gingold2020-04-011-11/+1
* synth: use more Dim_Type.Tristan Gingold2020-04-016-26/+27
* testsuite/synth: add a test for #1179Tristan Gingold2020-04-012-0/+26
* synth-static_oper: handle mul nat uns. Fix #1179Tristan Gingold2020-04-014-0/+47
* testsuite/synth: add test for #1180Tristan Gingold2020-04-012-0/+41
* synth: handle low/high type attributes. Fix #1180Tristan Gingold2020-04-011-0/+22
* vhdl-sem: add a todo note.Tristan Gingold2020-03-311-0/+1
* vhdl-sem_assocs: report all errors on incorrect formals.Tristan Gingold2020-03-311-1/+1
* netlists: add new helpers for yosys plugin.Tristan Gingold2020-03-313-3/+27
* synth-insts: keep module/generics/ports case for blackboxes.Tristan Gingold2020-03-311-23/+52
* netlists-disp_vhdl: display generics.Tristan Gingold2020-03-311-0/+25
* Makefile: Generate Param_Pval_* in ghdlsynth_gates.hTristan Gingold2020-03-313-1/+22
* synth: preliminary work to export module parameters.Tristan Gingold2020-03-319-26/+321
* options: handle -fmax-errors=Tristan Gingold2020-03-312-1/+9
* netlists-disp_vhdl: fix typos.Tristan Gingold2020-03-311-2/+2
* python: fix document URI creation on Windows (#1183)Maximilian Köstler2020-03-311-1/+1
* testsuite/synth: add test for #1178Tristan Gingold2020-03-302-0/+23
* synth: improve support of vhdl2008 aggregate targets. Fix #1178Tristan Gingold2020-03-303-53/+72
* testsuite/synth: add tests for #1177Tristan Gingold2020-03-303-0/+40
* synth: improve support of conditionnal operator. Fix #1177Tristan Gingold2020-03-301-1/+4
* synth: add helper to support inout ports in yosys plugin. For #1166Tristan Gingold2020-03-293-0/+18
* synth: improve output of memory initial value.Tristan Gingold2020-03-294-9/+82
* synth: add one more operation (or_reduce for suv).Tristan Gingold2020-03-291-1/+2
* testsuite/synth: add tests for #1175Tristan Gingold2020-03-294-0/+51
* synth: fix handling of subtype indication in object aliases for vhdl 2008.Tristan Gingold2020-03-292-5/+12
* testsuite/synth: add testcase for previous commit.Tristan Gingold2020-03-282-1/+20
* synth: handle or_reduce from std_logic_misc.Tristan Gingold2020-03-281-16/+10
* vhdl: recognize reduce functions in std_logic_misc.Tristan Gingold2020-03-285-1/+154
* synth-static_oper: add more operation.Tristan Gingold2020-03-281-0/+8
* netlists-memories: add flag_memory_verboseTristan Gingold2020-03-281-2/+7
* synth-oper: handle to_integer for signed.Tristan Gingold2020-03-281-0/+9
* synth: remove useless note message.Tristan Gingold2020-03-281-2/+5
* testsuite/synth: add testcase for #1069Tristan Gingold2020-03-289-0/+611
* synth: do not emit warning for unassigned but unused signals.Tristan Gingold2020-03-281-5/+11
* libraries/ieee: reimport std_logic_1164 from vhdl 2019Tristan Gingold2020-03-282-946/+1008
* netlists-dump: improve output.Tristan Gingold2020-03-281-6/+12
* synth: preliminary support of multiport rams (using shared variable).Tristan Gingold2020-03-286-333/+648
* synth-stmts: handle return from a function without a return.Tristan Gingold2020-03-271-2/+3
* synth: improve fatal error propagation.Tristan Gingold2020-03-272-0/+7
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