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author | Tristan Gingold <tgingold@free.fr> | 2020-03-31 18:26:11 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-31 18:29:06 +0200 |
commit | 643b474ce51021df3861a1c1251ebc61fb2851c6 (patch) | |
tree | 4e2679e3a6607d5d367904bee6ffc1d734ca6291 | |
parent | 86eb7790e833d2c93834901dcdf01aa89141c44c (diff) | |
download | ghdl-643b474ce51021df3861a1c1251ebc61fb2851c6.tar.gz ghdl-643b474ce51021df3861a1c1251ebc61fb2851c6.tar.bz2 ghdl-643b474ce51021df3861a1c1251ebc61fb2851c6.zip |
netlists-disp_vhdl: display generics.
-rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 957d1a3d0..13adbf62e 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -1394,6 +1394,29 @@ package body Netlists.Disp_Vhdl is end if; end Disp_Entity_Ports; + procedure Disp_Entity_Generics (M : Module) + is + Nbr : constant Param_Nbr := Get_Nbr_Params (M); + Desc : Param_Desc; + begin + if Nbr = 0 then + return; + end if; + for I in 1 .. Nbr loop + if I = 1 then + Put_Line (" generic ("); + else + Put_Line (";"); + end if; + Desc := Get_Param_Desc (M, I - 1); + Put (" "); + Put_Name (Desc.Name); + Put (" : "); + Put ("std_logic_vector"); + end loop; + Put_Line (");"); + end Disp_Entity_Generics; + procedure Disp_Entity (M : Module) is begin -- Module id and name. @@ -1405,6 +1428,8 @@ package body Netlists.Disp_Vhdl is Put_Name (Get_Module_Name (M)); Put_Line (" is"); + Disp_Entity_Generics (M); + Disp_Entity_Ports (M); Put ("end entity "); |