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* synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920Tristan Gingold2021-11-211-0/+7
* synth: put direction into port descTristan Gingold2021-11-178-31/+30
* synth: use a global table for instances attributesTristan Gingold2021-11-176-168/+117
* synth: renaming to instance_attributes.Tristan Gingold2021-11-1711-66/+72
* synth/netlists-disp_verilog: display port attributesTristan Gingold2021-11-171-18/+42
* synth: add ports attributesTristan Gingold2021-11-173-0/+120
* vhdl-utils.adb: minor refactoringTristan Gingold2021-11-171-7/+3
* grt: refactoring to fix build failure. For #1913Tristan Gingold2021-11-175-394/+443
* Add commentsTristan Gingold2021-11-172-0/+4
* vhdl-evaluation: use grt to compute value attribute for integers.Tristan Gingold2021-11-173-33/+97
* grt/Makefile.inc: add a dependency for grt-cgnatrts.Tristan Gingold2021-11-161-2/+3
* testsuite/synth: add a test for #1912Tristan Gingold2021-11-162-0/+82
* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-162-15/+110
* testsuite/gna: add scripts to generate 1d/2d aggregatesTristan Gingold2021-11-162-0/+30
* testsuite/gna: add a test for #1913Tristan Gingold2021-11-152-0/+123
* vhdl-evaluation: catch bad parameter for value attribute. Fix #1913Tristan Gingold2021-11-151-1/+7
* testsuite/gna: add a test for previous commitTristan Gingold2021-11-154-0/+83
* vhdl-sem_expr: improve code generation for multi-dim aggregatesTristan Gingold2021-11-151-3/+3
* testsuite/synth: add a test for syn_black_boxTristan Gingold2021-11-132-0/+23
* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
* testsuite/synth: add a test for #1911Tristan Gingold2021-11-133-0/+315
* synth: add exec_name_subtype. Fix #1911Tristan Gingold2021-11-133-4/+52
* testsuite/synth: add a test for black boxesTristan Gingold2021-11-124-0/+80
* testsuite/synth: adjust test after previous commitTristan Gingold2021-11-124-2/+20
* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
* std_names: add syn_black_boxTristan Gingold2021-11-123-182/+185
* testsuite/synth: add tests for rol/ror. For #1909Tristan Gingold2021-11-115-1/+85
* synth: also handle rol. For #1909Tristan Gingold2021-11-111-0/+5
* testsuite/synth: add a test for #1909Tristan Gingold2021-11-113-0/+67
* synth: handle ror from numeric_std. Fix #1909Tristan Gingold2021-11-111-1/+4
* vhdl: recognize ror/rol from ieee.numeric_std. For #1909Tristan Gingold2021-11-113-284/+304
* pyGHDL: regenerate nodes.pyTristan Gingold2021-11-101-309/+311
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-0924-667/+730
* lists: add a subtype for valid listsTristan Gingold2021-11-092-2/+4
* testsuite/gna: add a test for #1908Tristan Gingold2021-11-055-0/+573
* ghdlcomp: exit with error status in case of error. For #1908Tristan Gingold2021-11-051-0/+4
* vhdl-configuration: stop earlier in case of error. Fix #1908Tristan Gingold2021-11-051-17/+19
* testsuite/synth: add a test for #1899Tristan Gingold2021-11-052-0/+95
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-058-64/+143
* scripts/pnodes.py: add a commentTristan Gingold2021-11-051-0/+3
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-0411-739/+800
* vhdl: add tok_inherit. Preliminary work for #1899Tristan Gingold2021-11-037-740/+747
* testsuite/gna: add a test for #1898Tristan Gingold2021-11-035-0/+50
* trans-chap7: convert to base type for array-element operation. For #1898Tristan Gingold2021-11-031-3/+5
* ci: simplify MSYS2 matrices using 'pacboy'umarcor2021-11-031-44/+42
* synth: Support alias declarations in vunittmeissner2021-11-029-8/+55
* synth: do full elaboration before synthesisTristan Gingold2021-11-0161-2038/+5349
* testsuite/gna/issue1069: improve harnessTristan Gingold2021-11-011-1/+1
* vhdl: also warns on unused enumeration literalTristan Gingold2021-11-015-219/+256
* pyGHDL/cli/lsp.py: fix --disp-configTristan Gingold2021-11-011-0/+2
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