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* testsuite/gna: add a test for #1138Tristan Gingold2020-03-014-0/+133
* vhdl: a function call is not an object. Fix #1138.Tristan Gingold2020-03-013-15/+33
* vhdl-parse: avoid error cascade for 'subtype before 08.Tristan Gingold2020-03-011-1/+0
* synth: top entity name is not anymore hashed by default.Tristan Gingold2020-03-016-83/+138
* synth-insts: add comments, minor refactoring.Tristan Gingold2020-02-293-9/+6
* testsuite/synth: add test for #1146Tristan Gingold2020-02-292-0/+49
* synth: handle more physical operators. Fix #1146Tristan Gingold2020-02-294-21/+80
* synth-static_oper: handle enum inequality.Tristan Gingold2020-02-291-0/+3
* testsuite/synth: add a reproducer for tgingold/ghdlsynth-beta#87Tristan Gingold2020-02-293-0/+70
* synth-decls: fix handling of record subtypes.Tristan Gingold2020-02-291-1/+14
* Adjust version check in ci-run.shTristan Gingold2020-02-291-4/+5
* Set version to 1.0-devTristan Gingold2020-02-282-2/+2
* Release 0.37Tristan Gingold2020-02-283-3/+3
* vhdl-parse: improve error messages and recovery.Tristan Gingold2020-02-271-8/+46
* synth: handle file_close.Tristan Gingold2020-02-273-10/+31
* synth-static_oper: handle to_stdlogicvector_bvTristan Gingold2020-02-271-1/+20
* testsuite/synth: add a simple test for std_logic_arith.Tristan Gingold2020-02-272-0/+31
* std_logic_arith: comment out unused pragmas.Tristan Gingold2020-02-271-283/+283
* Update copyright years before the release.Tristan Gingold2020-02-264-30/+4
* testsuite/gna: add test for #1145Tristan Gingold2020-02-255-0/+79
* vhdl: handle CR+LF for readline in grt. Fix #1145Tristan Gingold2020-02-253-23/+65
* testsuite/synth: add test case for #1140Tristan Gingold2020-02-253-0/+118
* testsuites/synth: add missing files.Tristan Gingold2020-02-232-0/+97
* testsuite/synth: add tests for memory ports order.Tristan Gingold2020-02-233-2/+32
* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-237-46/+85
* netlists-memories: also reduce muxes for extract.Tristan Gingold2020-02-211-7/+35
* testsuite/synth: add a test for #1144Tristan Gingold2020-02-212-0/+25
* synth-decls: handle alias declaration without subtype indication.Tristan Gingold2020-02-211-2/+7
* testsuite/synth: add a source for mem01Tristan Gingold2020-02-202-0/+31
* netlists-memories: factorize code.Tristan Gingold2020-02-201-235/+191
* netlists-inference: preliminary work to support else in synch code.Tristan Gingold2020-02-201-71/+153
* netlists: add midffTristan Gingold2020-02-203-0/+47
* add build script for termux (#1143)umarcor2020-02-201-0/+15
* disable backtrace on android (#1142)umarcor2020-02-191-1/+1
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-187-417/+485
* synth: rework static predefined function calls.Tristan Gingold2020-02-183-152/+224
* synth: handle file_open.Tristan Gingold2020-02-183-0/+48
* testsuite/synth: adjust testcase #1078Tristan Gingold2020-02-181-1/+1
* synth-environment: handle unassigned outputs.Tristan Gingold2020-02-181-6/+8
* netlists-cleanup: refactoring.Tristan Gingold2020-02-181-12/+17
* testsuite/synth: add a test for previous commit.Tristan Gingold2020-02-183-1/+49
* synth-insts: handle slices in individual associations.Tristan Gingold2020-02-181-0/+21
* testsuite/synth: merge ram01 to mem01, add NOTES.txtTristan Gingold2020-02-189-17/+25
* testsuite/synth: add test for #1139Tristan Gingold2020-02-184-0/+149
* vhdl-sem_scopes: handle anonymous signal declarations.Tristan Gingold2020-02-181-1/+2
* vhdl-configuration: ignore configuration for top_level_entity.Tristan Gingold2020-02-181-4/+4
* synth-expr: handle anonymous signal declarations.Tristan Gingold2020-02-182-6/+10
* testsuite/gna: add tests for previous commit.Tristan Gingold2020-02-176-0/+168
* vhdl-sem_assocs: recurse for individual associations.Tristan Gingold2020-02-171-23/+64
* testsuite/synth: add a test for #1076Tristan Gingold2020-02-174-1/+156
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