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* synth: rework partial assignmentsTristan Gingold2019-08-2710-182/+608
* netlists-disp_vhdl: do not used literals for prefixes.Tristan Gingold2019-08-271-12/+53
* Makefile.in: Add .NOTPARALLEL. For #888Tristan Gingold2019-08-271-0/+9
* testsuite/synth: add fsm02 test.Tristan Gingold2019-08-275-0/+181
* ignore restrict in simulation (#897)Pepijn de Vos2019-08-202-18/+17
* synth: add support for constant exponentiation.Tristan Gingold2019-08-201-0/+10
* synth: set name to assert/assume gates.Tristan Gingold2019-08-204-12/+44
* netlist: fix minor pasto.Tristan Gingold2019-08-201-1/+1
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-207-6/+77
* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-207-67/+148
* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-08-202-0/+13
* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-203-13/+53
* vhdl-prints: handle verification units.Tristan Gingold2019-08-201-318/+354
* testsuite/synth: add a test for assume directive in verification units.Tristan Gingold2019-08-202-2/+11
* vhdl: handle assume in verification units.Tristan Gingold2019-08-205-1/+11
* testsuite/synth: add psl02Tristan Gingold2019-08-204-0/+74
* synth: analyze input files.Tristan Gingold2019-08-201-1/+8
* synth: set location on assume/assert gates.Tristan Gingold2019-08-203-8/+19
* synth: handle verification units.Tristan Gingold2019-08-2015-491/+703
* synth: handle array attribute "length" (#895)marph912019-08-191-0/+10
* synth: add testcase for issue 34Tristan Gingold2019-08-1713-0/+442
* synth: fix tgingold/ghdlsynth#34 (association).Tristan Gingold2019-08-171-2/+1
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-1716-605/+792
* testsuite/synth: add reproducer for tgingold/ghdlsynth-beta#33Tristan Gingold2019-08-163-0/+73
* synth: handle integer values in subtype conversion.Tristan Gingold2019-08-161-0/+2
* synth: handle integers for displaying vhdl ports.Tristan Gingold2019-08-161-0/+10
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-1615-759/+1061
* testsuite: strenghten a testcase.Tristan Gingold2019-08-161-0/+1
* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-169-737/+774
* testsuite/python: fix test name (to follow the testsuite.sh convention)Tristan Gingold2019-08-163-0/+0
* synth: handle array attributes; handle integer subtypes in generics.Tristan Gingold2019-08-162-2/+91
* Makefile.in: install synth include files as part of libghdl.Tristan Gingold2019-08-151-1/+6
* configure: complete --helpTristan Gingold2019-08-151-0/+2
* testsuite/synth: fix assert1 assertion.Tristan Gingold2019-08-151-1/+1
* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-155-7/+152
* synth: fix handling of assume/assert.Tristan Gingold2019-08-141-6/+65
* ghdlsynth: add command to get libghdl paths.Tristan Gingold2019-08-144-22/+97
* ghdldrv: move command_str_disp from ghdlvpi to ghdlmainTristan Gingold2019-08-143-38/+38
* testenv: also applies GHDL_FLAGS for synth.Tristan Gingold2019-08-141-1/+1
* ghdlsynth: declare init_for_ghdl_synth.Tristan Gingold2019-08-141-1/+4
* update NEWS.md. Fix #891Tristan Gingold2019-08-141-1/+8
* synth: add test for previous commit.Tristan Gingold2019-08-143-2/+29
* vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.Tristan Gingold2019-08-142-0/+12
* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-1410-242/+257
* testsuite/gna: use common testsuite.shTristan Gingold2019-08-141-14/+5
* testsuite/gna/README: document naming convention.Tristan Gingold2019-08-141-2/+11
* testsuite/gna: make testsuite.py neutral.Tristan Gingold2019-08-141-4/+1
* testsuite/gna: rename perf02 to not run it normally.Tristan Gingold2019-08-1436-0/+0
* testsuite/synth: make testsuite.sh more neutral.Tristan Gingold2019-08-141-2/+2