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* Add explicit ?>= and ?> functions for translation.Brian Padalino2021-09-226-4/+30
* Implement Matching Operators (#1872)Brian Padalino2021-09-221-8/+148
* testsuite/gna: add a test for #543Tristan Gingold2021-09-183-0/+38
* vhdl-evaluation.adb: handle iir_kind_aggregate in build_constant. Fix #543Tristan Gingold2021-09-181-0/+11
* vhdl-parse.adb: minor reformattingTristan Gingold2021-09-181-1/+2
* testsuite/gna: add a test for #1514Tristan Gingold2021-09-182-0/+22
* trans-chap8: fix iteration on an enumeration type with only one literal.Tristan Gingold2021-09-181-3/+9
* trans-chap8.adb: refactoring and clean-up. For #1514Tristan Gingold2021-09-182-46/+12
* vhdl-sem_names(sem_parenthesis_name): minor refactoringTristan Gingold2021-09-181-13/+9
* testsuite/gna: add a test for #1515Tristan Gingold2021-09-182-0/+21
* vhdl-sem_names(sem_parenthesis_name): handle indexing of delayed attribute.Tristan Gingold2021-09-181-2/+6
* configure and Makefile: link ghdl with grt-cstdioTristan Gingold2021-09-175-8/+13
* vhdl-evaluation.adb: fix warningTristan Gingold2021-09-171-3/+0
* testsuite/gna: add a test for #874Tristan Gingold2021-09-172-0/+39
* vhdl-evaluation: implement to_string for real with format. Fix #874Tristan Gingold2021-09-171-23/+69
* testsuite/gna: add a test and close #757Tristan Gingold2021-09-172-0/+22
* pyGHDL: added binding to new function 'Get_Source_Identifier' (#1870)Unai Martinez-Corral2021-09-162-2/+52
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| * Use new 'Get_Source_Identifier' in pyGHDL.DOM.Patrick Lehmann2021-09-161-2/+2
| * Added binding to new function 'Get_Source_Identifier'.Patrick Lehmann2021-09-161-0/+50
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* vhdl-utils: minor renaming for homogeneityTristan Gingold2021-09-162-2/+2
* testsuite/gna: add a test for #1857Tristan Gingold2021-09-163-0/+55
* trans-chap4: handle unbounded aggregate initial value to unbounded signal.Tristan Gingold2021-09-161-1/+30
* testsuite/gna: add a test for #1867Tristan Gingold2021-09-162-0/+47
* Fixed some typos (#1868)Patrick Lehmann2021-09-1611-22/+22
* netlists-disp_verilog: fix output of parameter assignments. Fix #1866Tristan Gingold2021-09-151-12/+12
* netlists-disp_verilog.adb: add 'parameter' before parameters declarationTristan Gingold2021-09-151-1/+1
* synth/netlists-disp_verilog: fix output of parameter values. For #1866Tristan Gingold2021-09-153-12/+37
* testsuite/gna: add a test and close #1495Tristan Gingold2021-09-152-0/+29
* vhdl: move Get_Source_Identifier to vhdl-utilsTristan Gingold2021-09-153-18/+25
* testsuite/gna: add a test for #1864Tristan Gingold2021-09-142-0/+30
* ortho_code-x86-insns: handle OE_ADD R_I_Off + R_I. Fix #1864Tristan Gingold2021-09-141-0/+7
* testsuite/gna: add a test and close #913Tristan Gingold2021-09-143-0/+51
* testsuite/gna: add a test and close #737Tristan Gingold2021-09-141-1/+2
* vhdl-sem_expr.adb: adjust aggregate element type extraction. For #737Tristan Gingold2021-09-141-2/+7
* testsuite/gna: add a test for #1493Tristan Gingold2021-09-142-0/+30
* trans-chap7: improve handling of vector in aggregates. Fix #1493Tristan Gingold2021-09-141-32/+58
* synth-vhdl_oper: handle nor for booleanTristan Gingold2021-09-141-0/+1
* trans-chap3: improve commentTristan Gingold2021-09-141-4/+4
* testsuite/gna: add a test for #1862Tristan Gingold2021-09-143-0/+78
* ortho: for slices, get element size from the result typeTristan Gingold2021-09-1410-17/+76
* add cpp header check for libghw (#1861)Matt Waltz2021-09-131-0/+9
* testsuite/gna: add a reproducer for #1453Tristan Gingold2021-09-123-0/+46
* trans-chap7: improve handling of vector in aggregates. Fix #1453Tristan Gingold2021-09-121-23/+27
* testsuite/gna: add a test for #786Tristan Gingold2021-09-122-0/+26
* trans-chap8: fix crash for slice in target aggregate. Fix #786Tristan Gingold2021-09-121-0/+4
* testsuite/gna: add a test for #873Tristan Gingold2021-09-122-0/+49
* vhdl-sem_assocs: add a check to avoid a crash on an error. Fix #873Tristan Gingold2021-09-121-0/+4
* vhdl-canon: recurse for default block configuration of a vunit.Tristan Gingold2021-09-122-19/+25
* testsuite/synth: add a test for previous commit (for #1860)Tristan Gingold2021-09-111-0/+1
* vhdl-configuration: also consider vunits to find top entity.Tristan Gingold2021-09-113-37/+64
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