testsuite/gna: add a test for #1857

3 files changed, 55 insertions, 0 deletions

diff --git a/testsuite/gna/issue1857/subtype_test.vhdl b/testsuite/gna/issue1857/subtype_test.vhdl
new file mode 100644
index 000000000..54a353c80
--- /dev/null
+++ b/testsuite/gna/issue1857/subtype_test.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity subtype_test is
+port
+(
+    i_Data : in  unsigned; -- (3 downto 0);
+    o_Data : out unsigned
+);
+end entity subtype_test;
+
+architecture RTL of subtype_test is
+
+-- signal Data : unsigned(i_Data'Range) := (others=>'0');
+signal Data : i_Data'subtype := (others=>'0');
+
+begin
+
+    Data   <= i_Data;
+    o_Data <= Data;
+
+end architecture RTL;
diff --git a/testsuite/gna/issue1857/tb.vhdl b/testsuite/gna/issue1857/tb.vhdl
new file mode 100644
index 000000000..9e24b01d2
--- /dev/null
+++ b/testsuite/gna/issue1857/tb.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--  A testbench has no ports.
+entity subtype_test_tb is
+end subtype_test_tb;
+
+architecture behav of subtype_test_tb is
+
+signal Data1 : unsigned (4-1 downto 0) := x"0";
+signal Data2 : unsigned (4-1 downto 0);
+
+begin
+    c_pwm : entity work.subtype_test
+        port map 
+        (
+            i_Data => Data1,
+            o_Data => Data2
+        );
+end behav;
diff --git a/testsuite/gna/issue1857/testsuite.sh b/testsuite/gna/issue1857/testsuite.sh
new file mode 100755
index 000000000..02d7fc235
--- /dev/null
+++ b/testsuite/gna/issue1857/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze subtype_test.vhdl tb.vhdl
+elab_simulate subtype_test_tb
+
+clean
+
+echo "Test successful"