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-rw-r--r--testsuite/synth/issue1198/for_loop.vhdl25
-rwxr-xr-xtestsuite/synth/issue1198/testsuite.sh9
2 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/synth/issue1198/for_loop.vhdl b/testsuite/synth/issue1198/for_loop.vhdl
new file mode 100644
index 000000000..4d1078dbd
--- /dev/null
+++ b/testsuite/synth/issue1198/for_loop.vhdl
@@ -0,0 +1,25 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity for_loop is
+ port(
+ a : in std_logic_vector(7 downto 0);
+ Count : out std_logic_vector(2 downto 0)
+ );
+end for_loop;
+
+architecture behavior of for_loop is
+begin
+ process(a)
+ variable Count_Aux : std_logic_vector(2 downto 0);
+ begin
+ Count_Aux := "000";
+ for i in a'range loop
+ if (a(i) = '0') then
+ Count_Aux := Count_Aux + 1;
+ end if;
+ end loop;
+ Count <= Count_Aux;
+ end process;
+end behavior;
diff --git a/testsuite/synth/issue1198/testsuite.sh b/testsuite/synth/issue1198/testsuite.sh
new file mode 100755
index 000000000..5d8015039
--- /dev/null
+++ b/testsuite/synth/issue1198/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=-fsynopsys
+synth_analyze for_loop
+clean
+
+echo "Test successful"