diff options
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/synth/psl01/cover3.vhdl | 20 | ||||
| -rwxr-xr-x | testsuite/synth/psl01/testsuite.sh | 3 |
2 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/psl01/cover3.vhdl b/testsuite/synth/psl01/cover3.vhdl new file mode 100644 index 000000000..59b70d7b6 --- /dev/null +++ b/testsuite/synth/psl01/cover3.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cover3 is + port ( + rst_n_i : in std_logic; + clk_i : in std_logic; + led0 : out std_logic + ); +end cover3; + +architecture top of cover3 is + signal led : std_logic_vector(7 downto 0); + -- Although not expected (there should be rising_edge), this was crashing. + default clock is clk_i; +begin + led0 <= led(0); + + cover { led(0) = '1' }; +end architecture top; diff --git a/testsuite/synth/psl01/testsuite.sh b/testsuite/synth/psl01/testsuite.sh index 7707566f7..fe19e38c6 100755 --- a/testsuite/synth/psl01/testsuite.sh +++ b/testsuite/synth/psl01/testsuite.sh @@ -8,6 +8,9 @@ for f in restrict1 restrict2 assume1 assume2 assert1 cover1 cover2; do synth -fpsl $f.vhdl -e $f > syn_$f.vhdl analyze syn_$f.vhdl done + +synth_failure cover3.vhdl -e cover3 + clean echo "Test successful" |