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-rw-r--r--testsuite/gna/ticket18/psl_test_error.vhd4
-rw-r--r--testsuite/gna/ticket18/psl_test_working.vhd4
-rw-r--r--testsuite/gna/ticket19/psl_test_cover.vhd4
-rw-r--r--testsuite/gna/ticket19/psl_test_cover2.vhd2
-rw-r--r--testsuite/gna/ticket19/psl_test_cover3.vhd2
5 files changed, 8 insertions, 8 deletions
diff --git a/testsuite/gna/ticket18/psl_test_error.vhd b/testsuite/gna/ticket18/psl_test_error.vhd
index aff436254..07a96d54f 100644
--- a/testsuite/gna/ticket18/psl_test_error.vhd
+++ b/testsuite/gna/ticket18/psl_test_error.vhd
@@ -42,7 +42,7 @@ begin
- -- psl statements
+ -- -psl statements
-- psl default clock is rising_edge(s_clk);
@@ -50,4 +50,4 @@ begin
-- psl assert always (s_write -> not(s_read)) report "ERROR: s_write and s_read active @ same time!";
-end architecture test; \ No newline at end of file
+end architecture test;
diff --git a/testsuite/gna/ticket18/psl_test_working.vhd b/testsuite/gna/ticket18/psl_test_working.vhd
index acb8aae1a..7939cffc6 100644
--- a/testsuite/gna/ticket18/psl_test_working.vhd
+++ b/testsuite/gna/ticket18/psl_test_working.vhd
@@ -42,7 +42,7 @@ begin
- -- psl statements
+ -- -psl statements
-- psl default clock is rising_edge(s_clk);
@@ -50,4 +50,4 @@ begin
-- psl assert always (s_write -> not(s_read));
-end architecture test; \ No newline at end of file
+end architecture test;
diff --git a/testsuite/gna/ticket19/psl_test_cover.vhd b/testsuite/gna/ticket19/psl_test_cover.vhd
index 4f3666f19..9fa73ec05 100644
--- a/testsuite/gna/ticket19/psl_test_cover.vhd
+++ b/testsuite/gna/ticket19/psl_test_cover.vhd
@@ -42,7 +42,7 @@ begin
- -- psl statements
+ -- -psl statements
-- psl default clock is rising_edge(s_clk);
@@ -50,4 +50,4 @@ begin
-- psl cover always (s_write -> not(s_read));
-end architecture test; \ No newline at end of file
+end architecture test;
diff --git a/testsuite/gna/ticket19/psl_test_cover2.vhd b/testsuite/gna/ticket19/psl_test_cover2.vhd
index 16d6ac810..000657d4c 100644
--- a/testsuite/gna/ticket19/psl_test_cover2.vhd
+++ b/testsuite/gna/ticket19/psl_test_cover2.vhd
@@ -49,7 +49,7 @@ begin
- -- psl statements
+ -- -psl statements
-- psl default clock is rising_edge(s_clk);
diff --git a/testsuite/gna/ticket19/psl_test_cover3.vhd b/testsuite/gna/ticket19/psl_test_cover3.vhd
index 0ef5d6ed9..260a47965 100644
--- a/testsuite/gna/ticket19/psl_test_cover3.vhd
+++ b/testsuite/gna/ticket19/psl_test_cover3.vhd
@@ -42,7 +42,7 @@ begin
- -- psl statements
+ --- psl statements
-- psl default clock is rising_edge(s_clk);