diff options
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/synth/issue1520/tb_test.vhdl | 94 | ||||
| -rw-r--r-- | testsuite/synth/issue1520/test.vhdl | 47 | ||||
| -rwxr-xr-x | testsuite/synth/issue1520/testsuite.sh | 8 |
3 files changed, 149 insertions, 0 deletions
diff --git a/testsuite/synth/issue1520/tb_test.vhdl b/testsuite/synth/issue1520/tb_test.vhdl new file mode 100644 index 000000000..59cfa7ce2 --- /dev/null +++ b/testsuite/synth/issue1520/tb_test.vhdl @@ -0,0 +1,94 @@ +entity tb_test is +end tb_test; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_test is + signal slv : std_logic_vector(7 downto 0); + signal sl : std_logic; + signal int : natural; + signal vec_scal_and : std_logic_vector(7 downto 0); + signal vec_scal_nand : std_logic_vector(7 downto 0); + signal vec_scal_or : std_logic_vector(7 downto 0); + signal vec_scal_nor : std_logic_vector(7 downto 0); + signal vec_scal_xor : std_logic_vector(7 downto 0); + signal vec_scal_xnor : std_logic_vector(7 downto 0); + signal scal_vec_and : std_logic_vector(7 downto 0); + signal scal_vec_nand : std_logic_vector(7 downto 0); + signal scal_vec_or : std_logic_vector(7 downto 0); + signal scal_vec_nor : std_logic_vector(7 downto 0); + signal scal_vec_xor : std_logic_vector(7 downto 0); + signal scal_vec_xnor : std_logic_vector(7 downto 0); + signal slv_sll : std_logic_vector(7 downto 0); + signal slv_srl : std_logic_vector(7 downto 0); +begin + dut: entity work.test + port map ( + slv => slv, + sl => sl, + int => int, + vec_scal_and => vec_scal_and, + vec_scal_nand => vec_scal_nand, + vec_scal_or => vec_scal_or, + vec_scal_nor => vec_scal_nor, + vec_scal_xor => vec_scal_xor, + vec_scal_xnor => vec_scal_xnor, + scal_vec_and => scal_vec_and, + scal_vec_nand => scal_vec_nand, + scal_vec_or => scal_vec_or, + scal_vec_nor => scal_vec_nor, + scal_vec_xor => scal_vec_xor, + scal_vec_xnor => scal_vec_xnor, + slv_sll => slv_sll, + slv_srl => slv_srl); + + process + begin + slv <= x"c5"; + sl <= '0'; + int <= 2; + + wait for 1 ns; + assert vec_scal_and = x"00" severity failure; + assert vec_scal_nand = x"ff" severity failure; + assert vec_scal_or = x"c5" severity failure; + assert vec_scal_nor = x"3a" severity failure; + assert vec_scal_xor = x"c5" severity failure; + assert vec_scal_xnor = x"3a" severity failure; + + assert scal_vec_and = x"00" severity failure; + assert scal_vec_nand = x"ff" severity failure; + assert scal_vec_or = x"c5" severity failure; + assert scal_vec_nor = x"3a" severity failure; + assert scal_vec_xor = x"c5" severity failure; + assert scal_vec_xnor = x"3a" severity failure; + + assert slv_sll = x"14" severity failure; + assert slv_srl = x"31" severity failure; + + + sl <= '1'; + int <= 3; + + wait for 1 ns; + assert vec_scal_and = x"c5" severity failure; + assert vec_scal_nand = x"3a" severity failure; + assert vec_scal_or = x"ff" severity failure; + assert vec_scal_nor = x"00" severity failure; + assert vec_scal_xor = x"3a" severity failure; + assert vec_scal_xnor = x"c5" severity failure; + + assert scal_vec_and = x"c5" severity failure; + assert scal_vec_nand = x"3a" severity failure; + assert scal_vec_or = x"ff" severity failure; + assert scal_vec_nor = x"00" severity failure; + assert scal_vec_xor = x"3a" severity failure; + assert scal_vec_xnor = x"c5" severity failure; + + assert slv_sll = x"28" severity failure; + assert slv_srl = x"18" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1520/test.vhdl b/testsuite/synth/issue1520/test.vhdl new file mode 100644 index 000000000..91bbc287d --- /dev/null +++ b/testsuite/synth/issue1520/test.vhdl @@ -0,0 +1,47 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test is + port ( + slv : in std_logic_vector(7 downto 0); + sl : in std_logic; + int : in natural; + + vec_scal_and : out std_logic_vector(7 downto 0); + vec_scal_nand : out std_logic_vector(7 downto 0); + vec_scal_or : out std_logic_vector(7 downto 0); + vec_scal_nor : out std_logic_vector(7 downto 0); + vec_scal_xor : out std_logic_vector(7 downto 0); + vec_scal_xnor : out std_logic_vector(7 downto 0); + + scal_vec_and : out std_logic_vector(7 downto 0); + scal_vec_nand : out std_logic_vector(7 downto 0); + scal_vec_or : out std_logic_vector(7 downto 0); + scal_vec_nor : out std_logic_vector(7 downto 0); + scal_vec_xor : out std_logic_vector(7 downto 0); + scal_vec_xnor : out std_logic_vector(7 downto 0); + + slv_sll : out std_logic_vector(7 downto 0); + slv_srl : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture arch of test is +begin + vec_scal_and <= slv and sl; + vec_scal_nand <= slv nand sl; + vec_scal_or <= slv or sl; + vec_scal_nor <= slv nor sl; + vec_scal_xor <= slv xor sl; + vec_scal_xnor <= slv xnor sl; + + scal_vec_and <= sl and slv; + scal_vec_nand <= sl nand slv; + scal_vec_or <= sl or slv; + scal_vec_nor <= sl nor slv; + scal_vec_xor <= sl xor slv; + scal_vec_xnor <= sl xnor slv; + + slv_sll <= slv sll int; + slv_srl <= slv srl int; +end architecture; diff --git a/testsuite/synth/issue1520/testsuite.sh b/testsuite/synth/issue1520/testsuite.sh new file mode 100755 index 000000000..e05dc42f2 --- /dev/null +++ b/testsuite/synth/issue1520/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_tb test + +echo "Test successful" |