5 files changed, 180 insertions, 0 deletions
diff --git a/testsuite/synth/synth14/repro.vhdl b/testsuite/synth/synth14/repro.vhdl
new file mode 100644
index 000000000..44ccf3650
--- /dev/null
+++ b/testsuite/synth/synth14/repro.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+  port (clk : std_logic;
+        rst : std_logic;
+        o : out std_logic);
+end repro;
+
+architecture behav of repro is
+  signal v : natural range 0 to 3;
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        v <= 0;
+      else
+        v <= v + 1;
+      end if;
+    end if;
+  end process;
+
+  o <= '1' when v = 0 else '0';
+end behav;
diff --git a/testsuite/synth/synth14/testsuite.sh b/testsuite/synth/synth14/testsuite.sh
new file mode 100755
index 000000000..7d1fdd888
--- /dev/null
+++ b/testsuite/synth/synth14/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth top_pkg.vhdl top.vhdl -e top > syn_top.vhdl
+analyze top_pkg.vhdl syn_top.vhdl
+clean
+
+echo "Test successful"
diff --git a/testsuite/synth/synth14/top.vhdl b/testsuite/synth/synth14/top.vhdl
new file mode 100644
index 000000000..c9925ee76
--- /dev/null
+++ b/testsuite/synth/synth14/top.vhdl
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.top_pack.all;
+
+entity top is port (
+   clk :  in std_logic;
+   D   : out std_logic_vector(1 to 5));
+end top;
+
+architecture beh of top is
+
+signal this_c : top_reg_t;
+signal this_r : top_reg_t;
+-- signal rst : std_logic := '0';
+
+begin
+   led : process(this_r, clk)
+   variable this : top_reg_t;
+   variable en : std_logic;
+   begin
+      this := this_r;
+
+      en := '0';
+      if this.prescale < 5000000 then en := '1'; end if;
+      this.y := to_slv(this.count, this.blip, en);
+
+      if this.prescale > 5999999 then
+         this.prescale := 0;
+         this.blip := '1';
+         if this.count = 3 then
+            this.count := 0;
+         else
+            this.count := this.count + 1;
+         end if;
+      else
+         if this.prescale = 1000000 then this.blip := '0'; end if;
+         this.prescale := this.prescale + 1;
+      end if;
+
+      this_c <= this;
+   end process;
+
+   led_r0 : process(clk)
+   begin
+     if clk = '1' and clk'event then
+         this_r <= this_c;
+      end if;
+   end process;
+
+   D <= this_r.y;
+end beh;
diff --git a/testsuite/synth/synth14/top.vhdl.orig b/testsuite/synth/synth14/top.vhdl.orig
new file mode 100644
index 000000000..b7fda8cf3
--- /dev/null
+++ b/testsuite/synth/synth14/top.vhdl.orig
@@ -0,0 +1,56 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.top_pack.all;
+
+entity top is port (
+   clk :  in std_logic;
+   D   : out std_logic_vector(1 to 5));
+end top;
+
+architecture beh of top is
+
+signal this_c : top_reg_t;
+signal this_r : top_reg_t;
+signal rst : std_logic := '0';
+
+begin
+   led : process(this_r, clk)
+   variable this : top_reg_t;
+   variable en : std_logic;
+   begin
+      this := this_r;
+
+      en := '0';
+      if this.prescale < 5000000 then en := '1'; end if;
+      this.y := to_slv(this.count, this.blip, en);
+
+      if this.prescale > 5999999 then
+         this.prescale := 0;
+         this.blip := '1';
+         if this.count = 3 then
+            this.count := 0;
+         else
+            this.count := this.count + 1;
+         end if;
+      else
+         if this.prescale = 1000000 then this.blip := '0'; end if;
+         this.prescale := this.prescale + 1;
+      end if;
+
+      this_c <= this;
+   end process;
+
+   led_r0 : process(clk, rst)
+   begin
+      if rst = '1' then
+         this_r <= TOP_REG_RESET;
+      elsif clk = '1' and clk'event then
+         this_r <= this_c;
+      end if;
+   end process;
+
+   D <= this_r.y;
+end beh;
diff --git a/testsuite/synth/synth14/top_pkg.vhdl b/testsuite/synth/synth14/top_pkg.vhdl
new file mode 100644
index 000000000..d2e182cbf
--- /dev/null
+++ b/testsuite/synth/synth14/top_pkg.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package top_pack is
+
+type top_reg_t is record
+  prescale : integer range 0 to (2**24)-1;
+  count    : integer range 0 to 3;
+  blip     : std_logic;
+  y        : std_logic_vector(1 to 5);
+end record;
+
+constant TOP_REG_RESET : top_reg_t := ( 0, 0, '0', (others => '0') );
+
+function to_slv(C:integer; B:std_logic; E:std_logic) return std_logic_vector;
+
+component top port (
+   clk :  in std_logic;
+   D   : out std_logic_vector(1 to 5));
+end component;
+
+end package;
+
+package body top_pack is
+
+function to_slv(C:integer; B:std_logic; E:std_logic) return std_logic_vector is
+variable ret : std_logic_vector(1 to 5) := (others => '0');
+begin
+   ret(C+1) := E;
+   ret(5)   := B;
+
+   return ret;
+end to_slv;
+
+end top_pack;