7 files changed, 202 insertions, 0 deletions
diff --git a/testsuite/synth/synth76/dff00.vhdl b/testsuite/synth/synth76/dff00.vhdl
new file mode 100644
index 000000000..b076f410c
--- /dev/null
+++ b/testsuite/synth/synth76/dff00.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff01 is
+  port (q : out std_logic_vector (3 downto 0);
+        d : std_logic_vector (3 downto 0);
+        en : std_logic;
+        rst : std_logic;
+        clk : std_logic);
+end dff01;
+
+architecture behav of dff01 is
+  signal t : std_logic_vector (7 downto 0);
+  signal a : std_logic_vector (3 downto 0);
+begin
+  a <= d xor b"0101";
+  
+  process (clk) is
+  begin
+    if rst = '1' then
+      q <= x"0";
+    elsif rising_edge (clk) then
+      if en = '1' then
+        q <= d;
+        t (7 downto 4) <= a;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth76/dff01.vhdl b/testsuite/synth/synth76/dff01.vhdl
new file mode 100644
index 000000000..b076f410c
--- /dev/null
+++ b/testsuite/synth/synth76/dff01.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff01 is
+  port (q : out std_logic_vector (3 downto 0);
+        d : std_logic_vector (3 downto 0);
+        en : std_logic;
+        rst : std_logic;
+        clk : std_logic);
+end dff01;
+
+architecture behav of dff01 is
+  signal t : std_logic_vector (7 downto 0);
+  signal a : std_logic_vector (3 downto 0);
+begin
+  a <= d xor b"0101";
+  
+  process (clk) is
+  begin
+    if rst = '1' then
+      q <= x"0";
+    elsif rising_edge (clk) then
+      if en = '1' then
+        q <= d;
+        t (7 downto 4) <= a;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth76/dff02.vhdl b/testsuite/synth/synth76/dff02.vhdl
new file mode 100644
index 000000000..bf2c70e14
--- /dev/null
+++ b/testsuite/synth/synth76/dff02.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff02 is
+  port (q : out std_logic;
+        d : std_logic;
+        en : std_logic;
+        rst : std_logic;
+        clk : std_logic);
+end dff02;
+
+architecture behav of dff02 is
+  signal t : std_logic := '1';
+begin
+  process (clk, rst) is
+  begin
+    if rst = '1' then
+      t <= '1';
+    elsif rising_edge (clk) then
+      if en = '1' then
+        t <= d;
+      end if;
+    end if;
+  end process;
+
+  q <= t;
+end behav;
diff --git a/testsuite/synth/synth76/dff03.vhdl b/testsuite/synth/synth76/dff03.vhdl
new file mode 100644
index 000000000..571f0f671
--- /dev/null
+++ b/testsuite/synth/synth76/dff03.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff03 is
+  port (q : out std_logic_vector (3 downto 0);
+        d : std_logic_vector (3 downto 0);
+        en : std_logic;
+        rst : std_logic;
+        clk : std_logic);
+end dff03;
+
+architecture behav of dff03 is
+  signal t : std_logic_vector (7 downto 4);
+  signal a : std_logic_vector (3 downto 0);
+begin
+  a <= d xor b"0101";
+  
+  process (clk) is
+  begin
+    if rst = '1' then
+      q <= x"0";
+    elsif rising_edge (clk) then
+      if en = '1' then
+        q <= d;
+        t (7 downto 4) <= a;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth76/dff04.vhdl b/testsuite/synth/synth76/dff04.vhdl
new file mode 100644
index 000000000..017f4f0c4
--- /dev/null
+++ b/testsuite/synth/synth76/dff04.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff04 is
+  port (q : out std_logic_vector (3 downto 0);
+        d : std_logic_vector (3 downto 0);
+        en : std_logic;
+        rst : std_logic;
+        clk : std_logic);
+end dff04;
+
+architecture behav of dff04 is
+begin
+  process (clk) is
+  begin
+    if rst = '0' then
+      null;
+    elsif rising_edge (clk) then
+      if en = '1' then
+        q <= d;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth76/tb_dff02.vhdl b/testsuite/synth/synth76/tb_dff02.vhdl
new file mode 100644
index 000000000..8f3ea5b2e
--- /dev/null
+++ b/testsuite/synth/synth76/tb_dff02.vhdl
@@ -0,0 +1,48 @@
+entity tb_dff02 is
+end tb_dff02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff02 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+  signal en : std_logic := '0';
+  signal rst : std_logic := '0';
+begin
+  dut: entity work.dff02
+    port map (
+      q => dout,
+      d => din,
+      en => en,
+      rst => rst,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    assert dout = '1' severity failure;
+    en <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+    en <= '1';
+    rst <= '1';
+    wait for 1 ns;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    rst <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth76/testsuite.sh b/testsuite/synth/synth76/testsuite.sh
new file mode 100755
index 000000000..387dee3a1
--- /dev/null
+++ b/testsuite/synth/synth76/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in dff02; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"