4 files changed, 75 insertions, 0 deletions
diff --git a/testsuite/synth/lib01/and2.vhdl b/testsuite/synth/lib01/and2.vhdl
new file mode 100644
index 000000000..e2d18ed02
--- /dev/null
+++ b/testsuite/synth/lib01/and2.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity and2 is
+  port (a, b : std_logic;
+        o : out std_logic);
+end and2;
+
+architecture behav of and2 is
+begin
+  o <= a and b;
+end behav;
diff --git a/testsuite/synth/lib01/and3.vhdl b/testsuite/synth/lib01/and3.vhdl
new file mode 100644
index 000000000..baf808e27
--- /dev/null
+++ b/testsuite/synth/lib01/and3.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+library mylib;
+
+entity and3 is
+  port (i0, i1, i2 : std_logic;
+        o : out std_logic);
+end and3;
+
+architecture behav of and3 is
+  signal t1 : std_logic;
+begin
+  a1: entity mylib.and2
+    port map (i0, i1, t1);
+  a2: entity mylib.and2
+    port map (t1, i2, o);
+end behav;
diff --git a/testsuite/synth/lib01/tb_and3.vhdl b/testsuite/synth/lib01/tb_and3.vhdl
new file mode 100644
index 000000000..3acf0c282
--- /dev/null
+++ b/testsuite/synth/lib01/tb_and3.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_and3 is
+end tb_and3;
+
+architecture behav of tb_and3 is
+  signal i0, i1, i2 : std_logic;
+  signal o : std_logic;
+
+begin
+  dut : entity work.and3
+    port map (i0 => i0, i1 => i1, i2 => i2, o => o);
+
+  process
+    constant v0 : std_logic_vector := b"1011";
+    constant v1 : std_logic_vector := b"1111";
+    constant v2 : std_logic_vector := b"1101";
+    constant ov : std_logic_vector := b"1001";
+  begin
+    for i in ov'range loop
+      i0 <= v0 (i);
+      i1 <= v1 (i);
+      i2 <= v2 (i);
+      wait for 1 ns;
+      assert o = ov(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/lib01/testsuite.sh b/testsuite/synth/lib01/testsuite.sh
new file mode 100755
index 000000000..621e78d14
--- /dev/null
+++ b/testsuite/synth/lib01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze --work=mylib and2.vhdl
+analyze and3.vhdl tb_and3.vhdl
+elab_simulate tb_and3
+clean
+
+synth --work=mylib and2.vhdl --work=work and3.vhdl -e and3 > syn_and3.vhdl
+analyze syn_and3.vhdl tb_and3.vhdl
+elab_simulate tb_and3
+clean
+clean mylib
+
+echo "Test successful"