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Diffstat (limited to 'testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams')
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1 files changed, 145 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams new file mode 100644 index 000000000..eb636b540 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams @@ -0,0 +1,145 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: generic_model.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- trying to check both ports and generics. +-- resistor component below has both port and generic. +-- same example as in mixed_mode_1 with ports +-- simulate for 2e10 +-- end comments by shishir. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use std.textio.all ; + +entity NOT_GATE is + generic ( delay : TIME := 100 ns ) ; + port ( + C : in bit; + Cbar : out bit); + +end NOT_GATE; + +architecture dataflow of NOT_GATE is + --signal my : bit := '0'; +begin -- dataflow + + Cbar <= not C after delay ; + +end dataflow ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +use std.textio.all; + +entity resistor is + generic ( resvalue : real := 100.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * resvalue ; +end behav; + +use work.electricalSystem.all; +use std.textio.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS + component NOT_GATE is + generic ( delay : TIME := 100 ns) ; + port ( + C : in bit; + Cbar : out bit); + end component ; + for all : NOT_GATE use entity work.NOT_GATE(dataflow) ; + + component resistor is + generic ( resvalue : real := 100.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + --QUANTITY vr1 ACROSS ir1 THROUGH n1 to n2; + --QUANTITY vr2 ACROSS ir2 THROUGH n2 ; + + signal y:bit:='0'; + +BEGIN + +-- digital component instantiation. + D2 : NOT_GATE generic map ( delay => 1000 ns) port map(C=>y, Cbar=>y); + + testbench:PROCESS + VARIABLE outline : LINE; + VARIABLE Headline : string(1 TO 8) := + "time y "; + VARIABLE seperator : string(1 TO 1) := " "; + VARIABLE flag : bit := '0'; + FILE outfile: text OPEN WRITE_MODE IS "generic_model.out"; + BEGIN + IF (flag = '0') THEN + flag := '1'; + WRITE(outline,Headline); + WRITELINE(outfile,outline); + ELSE + WRITE(outline, now); + WRITE(outline,seperator); + WRITE(outline,y); + WRITE(outline,seperator); + writeline(outfile,outline); + END IF; + WAIT ON y; + END PROCESS; + +-- analog component instantiation. +-- for some strange reason if i put it above the process, it does not work. + + R1 : resistor generic map ( resvalue => 500.0) port map (P => n1, N => n2); + --R1 : resistor port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); +-- R1 : vr1 == ir1 * 100.0 ; + -- R2 : vr2 == ir2 * 100.0 ; + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; |