1 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd
new file mode 100644
index 000000000..ba0d4a0b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_12.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity counter is
+
+  generic ( tipd_reset,                   -- input prop delay on reset
+            tipd_clk,                     -- input prop delay on clk
+            topd_q : delay_length;        -- output prop delay on q
+            tsetup_reset,                 -- setup: reset before clk
+            thold_reset : delay_length ); -- hold time: reset after clk
+
+  port ( reset,                           -- synchronous reset input
+         clk : in bit;                    -- edge triggered clock input
+         q : out bit_vector );            -- counter output
+
+end entity counter;