1 files changed, 46 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd
new file mode 100644
index 000000000..cfd5862e6
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+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behav of reg4 is
+begin
+
+  storage : process is
+                      variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
+  begin 
+    if en = '1' and clk = '1' then
+      stored_d0 := d0;
+      stored_d1 := d1;
+      stored_d2 := d2;
+      stored_d3 := d3;
+    end if;
+    q0 <= stored_d0 after 5 ns;
+    q1 <= stored_d1 after 5 ns;
+    q2 <= stored_d2 after 5 ns;
+    q3 <= stored_d3 after 5 ns;
+    wait on d0, d1, d2, d3, en, clk;
+  end process storage;
+
+end architecture behav;