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-rw-r--r--testsuite/synth/synth58/repro1.vhdl26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/synth58/repro1.vhdl b/testsuite/synth/synth58/repro1.vhdl
new file mode 100644
index 000000000..391017cf3
--- /dev/null
+++ b/testsuite/synth/synth58/repro1.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+
+entity repro1 is
+ generic (
+ g : std_logic := '1'
+ );
+ port (
+ i : in std_logic_vector(7 downto 0);
+ o : out std_logic_vector(7 downto 0)
+ );
+end repro1;
+
+architecture rtl of repro1 is
+begin
+ process (i)
+ variable slv_out : std_logic_vector(7 downto 0);
+ begin
+ if g = '0' then
+ slv_out := i;
+ elsif g = '1' then
+ slv_out := not i;
+ end if;
+ o <= slv_out;
+ end process;
+end rtl;