1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/synth/synth45/test.vhdl b/testsuite/synth/synth45/test.vhdl
new file mode 100644
index 000000000..6d495c826
--- /dev/null
+++ b/testsuite/synth/synth45/test.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+end entity test;
+
+architecture beh of test is
+
+  type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
+  signal s_register : t_register;
+
+begin
+
+  -- the problem is the next line
+  s_register  <= (others => (others => '0'));
+
+end architecture beh;