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-rw-r--r--testsuite/synth/mem01/sram05.vhdl34
1 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/synth/mem01/sram05.vhdl b/testsuite/synth/mem01/sram05.vhdl
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+++ b/testsuite/synth/mem01/sram05.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sram05 is
+ port (
+ rst : std_logic;
+ clk_i : std_logic;
+ addr_i : std_logic_vector(3 downto 0);
+ data_i : std_logic_vector(7 downto 0);
+ data_o : out std_logic_vector(7 downto 0);
+ wen_i : std_logic);
+end sram05;
+
+architecture behav of sram05 is
+begin
+ process (clk_i, addr_i)
+ type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
+ variable mem : mem_type;
+ variable addr : natural range mem_type'range;
+ begin
+ if rising_edge(clk_i) then
+ if rst = '1' then
+ null;
+ else
+ addr := to_integer (unsigned (addr_i));
+ if wen_i = '1' then
+ mem (addr) := data_i;
+ end if;
+ data_o <= mem (addr);
+ end if;
+ end if;
+ end process;
+end behav;