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Diffstat (limited to 'testsuite/synth/issue951/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue951/ent.vhdl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/issue951/ent.vhdl b/testsuite/synth/issue951/ent.vhdl new file mode 100644 index 000000000..1d6ae9a72 --- /dev/null +++ b/testsuite/synth/issue951/ent.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + clk : in std_logic; + enable : in std_logic; + i : in std_logic; + o : out std_logic + ); +end; + +architecture a of ent is +begin + process(clk) + begin + -- works: + --if rising_edge(clk) and enable = '1' then + if enable = '1' and rising_edge(clk) then + o <= i; + end if; + end process; +end; |