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Diffstat (limited to 'testsuite/synth/issue946/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue946/ent.vhdl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/issue946/ent.vhdl b/testsuite/synth/issue946/ent.vhdl new file mode 100644 index 000000000..a63db2903 --- /dev/null +++ b/testsuite/synth/issue946/ent.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + i : in bit; + o : out bit + ); +end; + +architecture a of ent is + signal test : std_logic_vector(7 downto 0); + alias a : std_logic_vector(3 downto 0) is test(7 downto 4); +begin + process(i) + begin + case a(1 downto 0) is + when others => + end case; + + o <= i; + end process; +end; |