3 files changed, 63 insertions, 1 deletions
diff --git a/testsuite/synth/issue662/psl_rose.vhdl b/testsuite/synth/issue662/psl_rose.vhdl
new file mode 100644
index 000000000..83e9a6c04
--- /dev/null
+++ b/testsuite/synth/issue662/psl_rose.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity psl_rose is
+  port (clk, a, b : in std_logic
+  );
+end entity psl_rose;
+
+
+architecture psl of psl_rose is
+begin
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  ROSE_0_a : assert always {not a; a} |-> rose(a);
+
+  -- This assertion holds
+  ROSE_1_a : assert always (rose(a) -> (prev(a) = '0' and a = '1'));
+
+  -- This assertion should fail at cycle 11
+  ROSE_2_a : assert always rose(a) -> b;
+
+end architecture psl;
diff --git a/testsuite/synth/issue662/tb_psl_rose.vhdl b/testsuite/synth/issue662/tb_psl_rose.vhdl
new file mode 100644
index 000000000..80babc56e
--- /dev/null
+++ b/testsuite/synth/issue662/tb_psl_rose.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity tb_psl_rose is
+end entity tb_psl_rose;
+
+
+architecture psl of tb_psl_rose is
+
+  procedure seq (s : string; signal clk : std_logic; signal o : out std_logic)
+  is
+  begin
+    for i in s'range loop
+      wait until rising_edge(clk);
+      case s(i) is
+        when '0' | '_' => o <= '0';
+        when '1' | '-' => o <= '1';
+        when others    => o <= 'X';
+      end case;
+    end loop;
+    wait;
+  end seq;
+
+  signal a, b : std_logic := '0';
+  signal clk  : std_logic := '1';
+
+begin
+
+  dut: entity work.psl_rose port map (clk, a, b);
+
+  clk <= not clk after 500 ps;
+
+  --             012345678901234
+  SEQ_A :  seq ("__-__---___--__", clk, a);
+  SEQ_B :  seq ("__-__-______-__", clk, b);
+
+end architecture psl;
diff --git a/testsuite/synth/issue662/testsuite.sh b/testsuite/synth/issue662/testsuite.sh
index 62e06f718..1047b853e 100755
--- a/testsuite/synth/issue662/testsuite.sh
+++ b/testsuite/synth/issue662/testsuite.sh
@@ -4,7 +4,7 @@
 
 GHDL_STD_FLAGS=--std=08
 
-for test in psl_prev psl_stable; do
+for test in psl_prev psl_stable psl_rose; do
   synth_analyze $test
   analyze tb_${test}.vhdl
   elab_simulate_failure tb_${test} --stop-time=20ns --asserts=disable-at-0 --assert-level=error