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-rw-r--r--testsuite/synth/issue34/submodule.vhdl20
1 files changed, 0 insertions, 20 deletions
diff --git a/testsuite/synth/issue34/submodule.vhdl b/testsuite/synth/issue34/submodule.vhdl
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index bc282985a..000000000
--- a/testsuite/synth/issue34/submodule.vhdl
+++ /dev/null
@@ -1,20 +0,0 @@
-library ieee;
- use ieee.std_logic_1164.all;
-
-entity submodule is
- port (
- clk : in std_logic;
- a : in std_logic_vector(7 downto 0);
- b : out std_logic_vector(7 downto 0)
- );
-end submodule;
-
-architecture rtl of submodule is
-begin
- process(clk)
- begin
- if rising_edge(clk) then
- b <= a;
- end if;
- end process;
-end rtl;