diff options
Diffstat (limited to 'testsuite/synth/issue2146')
-rw-r--r-- | testsuite/synth/issue2146/rom_test.vhdl | 58 | ||||
-rwxr-xr-x | testsuite/synth/issue2146/testsuite.sh | 11 |
2 files changed, 69 insertions, 0 deletions
diff --git a/testsuite/synth/issue2146/rom_test.vhdl b/testsuite/synth/issue2146/rom_test.vhdl new file mode 100644 index 000000000..e5c2917f3 --- /dev/null +++ b/testsuite/synth/issue2146/rom_test.vhdl @@ -0,0 +1,58 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity rom_test is + generic ( + CONFIG : std_ulogic_vector(0 to 7) + ); + port ( + clk : in std_ulogic; + reset_n : in std_ulogic; + valid : out std_ulogic + ); +end rom_test; + +architecture struct of rom_test is + type entry_t is record + value : unsigned(7 downto 0); + valid : std_ulogic; + end record; + + type rom_t is array(natural range<>) of entry_t; + + function generate_rom(input : std_ulogic_vector) return rom_t is + variable ret : rom_t(0 to input'length-1); + begin + for i in input'range loop + ret(i).valid := input(i); + if input(i) = '1' then + ret(i).value := to_unsigned(i, 8); + end if; + end loop; + return ret; + end function; + + constant ROM : rom_t := generate_rom(CONFIG); + + signal index : natural range 0 to ROM'length-1; + signal entry : entry_t; + +begin + process(clk, reset_n) + begin + if reset_n = '0' then + index <= 0; + elsif rising_edge(clk) then + if index = ROM'length-1 then + index <= 0; + else + index <= index + 1; + end if; + end if; + end process; + + entry <= ROM(index); + valid <= entry.valid; + +end architecture; diff --git a/testsuite/synth/issue2146/testsuite.sh b/testsuite/synth/issue2146/testsuite.sh new file mode 100755 index 000000000..4aec48ee6 --- /dev/null +++ b/testsuite/synth/issue2146/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_SYNTH_FLAGS=-gCONFIG="10111011" +synth_analyze rom_test 2> synth.log +grep "found ROM" synth.log + +clean + +echo "Test successful" |