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-rw-r--r--testsuite/synth/issue2145/bug.vhdl39
1 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/synth/issue2145/bug.vhdl b/testsuite/synth/issue2145/bug.vhdl
new file mode 100644
index 000000000..749ab78c5
--- /dev/null
+++ b/testsuite/synth/issue2145/bug.vhdl
@@ -0,0 +1,39 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity sub is
+ generic(
+ WIDTH : positive := 32
+ );
+ port (
+ data : out std_ulogic_vector(WIDTH-1 downto 0)
+ );
+end sub;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity bug is
+ generic(
+ WIDTH : positive := 32
+ );
+ port (
+ data : out std_ulogic_vector(WIDTH-1 downto 0)
+ );
+end bug;
+
+architecture struct of sub is
+begin
+ data <= (others => '0');
+end architecture;
+
+architecture struct of bug is
+begin
+ base: entity work.sub
+ generic map(
+ WIDTH => WIDTH
+ )
+ port map(
+ data => data
+ );
+end architecture;