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-rw-r--r--testsuite/synth/issue1675/patgen.vhdl38
1 files changed, 38 insertions, 0 deletions
diff --git a/testsuite/synth/issue1675/patgen.vhdl b/testsuite/synth/issue1675/patgen.vhdl
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+++ b/testsuite/synth/issue1675/patgen.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pkg.all;
+
+entity patgen is
+ port (
+ clk : std_logic;
+ rst : std_logic;
+ bo : out bus_rec_out_t);
+end patgen;
+
+architecture behav of patgen is
+ signal cnt : unsigned(1 downto 0);
+begin
+ with cnt select
+ bo.dat <= x"01" when "00",
+ x"02" when "01",
+ x"03" when "10",
+ x"05" when "11",
+ x"00" when others;
+
+ bo.rst <= rst;
+ bo.stb <= not rst;
+
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ cnt <= "00";
+ else
+ cnt <= cnt + 1;
+ end if;
+ end if;
+ end process;
+end behav;
+