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-rw-r--r--testsuite/synth/issue1319/ent.vhdl55
-rw-r--r--testsuite/synth/issue1319/repro.vhdl52
-rw-r--r--testsuite/synth/issue1319/repro2.vhdl30
-rw-r--r--testsuite/synth/issue1319/repro3.vhdl27
-rw-r--r--testsuite/synth/issue1319/tb_ent.vhdl33
-rwxr-xr-xtestsuite/synth/issue1319/testsuite.sh8
6 files changed, 205 insertions, 0 deletions
diff --git a/testsuite/synth/issue1319/ent.vhdl b/testsuite/synth/issue1319/ent.vhdl
new file mode 100644
index 000000000..4e7960724
--- /dev/null
+++ b/testsuite/synth/issue1319/ent.vhdl
@@ -0,0 +1,55 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity ent is
+ port (
+ insn_i : in std_ulogic_vector(31 downto 0);
+ ispr1_o : out std_ulogic_vector(5 downto 0);
+ ispr2_o : out std_ulogic_vector(5 downto 0)
+ );
+end entity ent;
+
+architecture behaviour of ent is
+ -- SPR numbers
+ subtype spr_num_t is integer range 0 to 1023;
+
+ function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
+
+ constant SPR_XER : spr_num_t := 1;
+ constant SPR_LR : spr_num_t := 8;
+ constant SPR_CTR : spr_num_t := 9;
+
+ -- Extended GPR indice (can hold an SPR)
+ subtype gspr_index_t is std_ulogic_vector(5 downto 0);
+
+ function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
+ begin
+ return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
+ end;
+ function fast_spr_num(spr: spr_num_t) return gspr_index_t is
+ variable n : integer range 0 to 31;
+ begin
+ case spr is
+ when SPR_LR =>
+ n := 0;
+ when SPR_CTR =>
+ n:= 1;
+ when SPR_XER =>
+ n := 12;
+ when others =>
+ n := 0;
+ return "000000";
+ end case;
+ return "1" & std_ulogic_vector(to_unsigned(n, 5));
+ end;
+
+begin
+ decode1_1: process(all)
+ begin
+ ispr1_o <= fast_spr_num(decode_spr_num(insn_i));
+ ispr2_o <= fast_spr_num(SPR_XER);
+ end process;
+end architecture behaviour;
diff --git a/testsuite/synth/issue1319/repro.vhdl b/testsuite/synth/issue1319/repro.vhdl
new file mode 100644
index 000000000..3783b1a63
--- /dev/null
+++ b/testsuite/synth/issue1319/repro.vhdl
@@ -0,0 +1,52 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity repro is
+ port (
+ insn_i : in std_ulogic_vector(31 downto 0);
+ ispr1_o : out std_ulogic_vector(5 downto 0);
+ spr_o : out std_ulogic_vector (9 downto 0)
+ );
+end entity repro;
+
+architecture behaviour of repro is
+ -- SPR numbers
+ subtype spr_num_t is integer range 0 to 1023;
+
+ function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
+
+ constant SPR_XER : spr_num_t := 1;
+ constant SPR_LR : spr_num_t := 8;
+ constant SPR_CTR : spr_num_t := 9;
+
+ -- Extended GPR indice (can hold an SPR)
+ subtype gspr_index_t is std_ulogic_vector(5 downto 0);
+
+ function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
+ begin
+ return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
+ end;
+ function fast_spr_num(spr: spr_num_t) return gspr_index_t is
+ variable n : integer range 0 to 31;
+ begin
+ case spr is
+ when SPR_LR =>
+ n := 0;
+ when SPR_CTR =>
+ n:= 1;
+ when SPR_XER =>
+ n := 12;
+ when others =>
+ n := 0;
+ return "000000";
+ end case;
+ return "1" & std_ulogic_vector(to_unsigned(n, 5));
+ end;
+
+begin
+ ispr1_o <= fast_spr_num(decode_spr_num(insn_i));
+ spr_o <= std_ulogic_vector (to_unsigned (decode_spr_num(insn_i), 10));
+end architecture behaviour;
diff --git a/testsuite/synth/issue1319/repro2.vhdl b/testsuite/synth/issue1319/repro2.vhdl
new file mode 100644
index 000000000..7872e1163
--- /dev/null
+++ b/testsuite/synth/issue1319/repro2.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity repro2 is
+ port (
+ i : in std_ulogic_vector(1 downto 0);
+ o : out std_ulogic_vector (3 downto 0)
+ );
+end entity repro2;
+
+architecture behav of repro2 is
+ function func (v : std_ulogic_vector (1 downto 0)) return std_ulogic_vector is
+ variable res : std_ulogic_vector (3 downto 0);
+ begin
+ case v is
+ when "01" =>
+ res := "1111";
+ when others =>
+ res := "0000";
+ return "0000";
+ end case;
+ return res;
+ end;
+
+begin
+ o <= func (i);
+end architecture behav;
diff --git a/testsuite/synth/issue1319/repro3.vhdl b/testsuite/synth/issue1319/repro3.vhdl
new file mode 100644
index 000000000..ab578598c
--- /dev/null
+++ b/testsuite/synth/issue1319/repro3.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity repro3 is
+ port (
+ i : in std_ulogic_vector(1 downto 0);
+ o : out std_ulogic_vector (3 downto 0)
+ );
+end entity repro3;
+
+architecture behav of repro3 is
+ function func (v : std_ulogic_vector (1 downto 0)) return std_ulogic_vector is
+ begin
+ case v is
+ when "01" =>
+ null;
+ when others =>
+ return "0000";
+ end case;
+ return "1111";
+ end;
+begin
+ o <= func (i);
+end architecture behav;
diff --git a/testsuite/synth/issue1319/tb_ent.vhdl b/testsuite/synth/issue1319/tb_ent.vhdl
new file mode 100644
index 000000000..db690ddf5
--- /dev/null
+++ b/testsuite/synth/issue1319/tb_ent.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity tb_ent is
+end tb_ent;
+
+architecture behave of tb_ent is
+ signal insn: std_ulogic_vector(31 downto 0);
+ signal ispr1: std_ulogic_vector(5 downto 0);
+ signal ispr2: std_ulogic_vector(5 downto 0);
+begin
+ test: entity work.ent
+ port map (
+ insn_i => insn,
+ ispr1_o => ispr1,
+ ispr2_o => ispr2
+ );
+
+ test_process: process
+ begin
+ insn <= x"7d8903a6";
+ wait for 1 ns;
+ report " ispr1=" & to_hstring(ispr1);
+ report " ispr2=" & to_hstring(ispr2);
+ assert ispr1 = 6x"21" severity failure;
+ assert ispr2 = 6x"2c" severity failure;
+ report "end of test";
+ wait;
+ end process;
+end behave;
diff --git a/testsuite/synth/issue1319/testsuite.sh b/testsuite/synth/issue1319/testsuite.sh
new file mode 100755
index 000000000..78f25565d
--- /dev/null
+++ b/testsuite/synth/issue1319/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_tb ent
+
+echo "Test successful"