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-rw-r--r--testsuite/synth/issue1208/adders_4.vhdl21
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue1208/adders_4.vhdl b/testsuite/synth/issue1208/adders_4.vhdl
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+++ b/testsuite/synth/issue1208/adders_4.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity adders_4 is
+ port(A,B : in std_logic_vector(7 downto 0);
+ CI : in std_logic;
+ SUM : out std_logic_vector(7 downto 0);
+ CO : out std_logic);
+end adders_4;
+
+architecture archi of adders_4 is
+ signal tmp: std_logic_vector(8 downto 0);
+begin
+
+ tmp <= conv_std_logic_vector((conv_integer(A) + conv_integer(B) + conv_integer(CI)),9);
+ SUM <= tmp(7 downto 0);
+ CO <= tmp(8);
+
+end archi;