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-rw-r--r--testsuite/synth/issue1096/tb_my_entity.vhdl19
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/synth/issue1096/tb_my_entity.vhdl b/testsuite/synth/issue1096/tb_my_entity.vhdl
new file mode 100644
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--- /dev/null
+++ b/testsuite/synth/issue1096/tb_my_entity.vhdl
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+entity tb_my_entity is
+end tb_my_entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_my_entity is
+ signal a : std_logic_vector(0 downto 0);
+begin
+ dut: entity work.my_entity
+ port map (a);
+
+ process
+ begin
+ wait for 1 ns;
+ assert a = "0" severity failure;
+ wait;
+ end process;
+end behav;